If you go to nvidia's jobs website today you'll find they're actively hiring FPGA developers for ASIC prototyping. Obviously they're not dumping their 5090 RTL straight into some 10 metre wide FPGA chip. First, they grab the largest FPGA you can get your hands on - the FPGA vendors tend to have a couple of comically expensive comically large SKUs for specifically this purpose. Then you pop a few of them onto a development board and partition your design across the cluster of FPGAs with some custom interconnect, orchestration and DFT stuff. FPGAs offer quite a compelling way of getting test mileage vs simuluation/emulation in software.

Every. If I was to guess, NVidia probably uses Cadence Palladium/Protium solutions[1]. They're basically industry standard, and essentially everyone uses Cadence design tools for circuit design.

[1]: https://www.cadence.com/en_US/home/tools/system-design-and-v...

You don't need to simulate the design completely/simultaneously. The FPGA sim implementation might only contain 1 CUDA SM, for instance.

For large ASIC designs like this, companies often use numerous (12+) FPGAs connected via transceivers on dedicated simulation boards.