Transient execution CPU vulnerability: https://en.wikipedia.org/wiki/Transient_execution_CPU_vulner...
Does RISC-V have speculative execution?
A RISC-V CPU out of graphene would be more efficient.
There are various optional feature flags for RISC-V.
The RISC-V open ISA is probably advantageous especially for research implementations.
https://libre-chip.org/first_arch/index.html
https://web.archive.org/web/20201021124234/https://bugs.libr...
https://web.archive.org/web/20240610080828/https://groups.go...
https://danluu.com/branch-prediction/
> One idea I had for making a spectre-proof speculative execution engine is to build a theoretical model CPU such that it compares a branch oracle to the results of its branch prediction unit and takes the amount of time needed by the misprediction penalty when the branch predictor mispredicts, but doesn't actually execute any mispredicted instructions. This makes the model CPU unable to have spectre-style vulnerabilities since it doesn't do any actual speculative execution.
> Then, a physical CPU is built using the exact same design (where every instruction and every cache state change completes at the exact same clock cycle as the corresponding instruction in the theoretical model) but using speculative execution instead of the branch oracle. This gives a physical cpu that can be proven to not have any timing vulnerabilities that the model CPU doesn't have (ruling out spectre-style vulnerabilities) by proving that it follows the same steps as the model CPU.
dutchmartin•5mo ago