> The only thing left to do was solder it up (not trivial, given that I’m trying to hit a 250 μm diameter target at the bottom of a 1.6mm deep hole).

Shiiiit, absolutely heroic skill level.

I imagine he'll post the files, so they won't be a one-off.

This one is especially tricky since even if you know what a phased lock loop (PLL) is, the terms CPLL and QPLL are specific to the arrangement of transceivers in these specific Xilinx FPGAs (7 series being one family of FPGAs which came before the UltraScale and then UltraScale+ series). There are four transceivers in a ‘quad’ which can either run from their ‘Channel PLL’ (CPLL) or the shared ‘Quad PLL’ that can run much faster to do basically double the line rate.

You could build an NTP server with much less horsepower (and of course without all of the high speed I/O etc).

The ones from Leo Bodnar are decent.