So reading, the citation fully, it seems that Furber doesn't really dive deep into the ARM1, instead saving a deep dive for the ARM2 as well as an additional chapter about the changes then made for the ARM3. I think kens might be steel manning the position.

> In theory PLAs and ROMs are fully equivalent. In practice, while the ROM can accept any possible "microcode", a PLA might have to be enlarged if you want to change some of the "micro instruction". This need to change the hardware to change the functionality of an instruction is what makes me consider this design hardwired instead of microcoded.

Traditionally, the difference would be defined as whether or not it's structured as an address being decoded to create a one hot enable signal for a single row of the array at a time. When you take the FSM signals as a sub address, and the init, interrupt, and decoded instr bits as a segment address, this is what you see here. And that matches the structure seen in traditional CISC microcode ROMs.

Additionally, there is extra space on the die for an additional few rows.

> [EDIT] Another issue is that the ARM1 has three pipeline stages. The "microcode" here is not used for the fetch and decode stages, only the execute one. So though register to register operations take 3 clock cycles to execute, only one "micro instruction" is needed (the second line in the table).

The pipelining doesn't really matter here. The 486 for instance more or less completed one (simple) instruction a clock, but had a rather deep for the time piepline where those instructions would have several cycles of latency. Those simple instructions were also a single micro op despite being being processed in several pipeline stages. And the micro decode was not the first stage of the pipeline either. The 486 had a deeper pipeline with fetch, decode 1, decode 2, execute, and writeback pipeline stages, but didn't start emitting micro instructions except as the output of the third pipeline stage.