A lot of my questions went away when I got to this line though:

> He’s also fully engaged in the third leg of the “democratizing chip design” stool: education.

This is a valiant effort. Chip design is a hard world to break into, and many applications that could benefit from ASICs aren't iterating or testing on it because it sucks to do. It's a lot of work to bring that skill ceiling down, but as a programmer I could see how an LLVM-style intermediate representation layer could help designers get up-and-running faster.

Basically.

Improving the lived experience keeping it real! Feels so much more authentic.

More people would love AI if it communicated like an emo *Nix elitist. Train it on Daria, Eeyore, and grunge lyrics! People will love it!

The difficulty is not (entirely) technical

Perhaps it's the first open one. I was an eng manager at a hyperscaler helping one of our clients, a large semiconductor design company, build models to use internally. It was trained on their extensive Verilog repos, tooling, and strict style guides. I see this being repeated across industries, at least since 2023 there are quite a few deep-pocketed S&P 500 orgs creating models from scratch or extensively finetuning to give unique advantages they require. They're rarely announced specifically, but you can often infer from the initial investment or partnership announcements that they're working on it.