> Until now, most attempts at 3D chips have relied on stacking separate chips. That approach works, but the connections between layers are coarse, sparse, and prone to bottlenecks.
> Instead of fabricating separate chips and then fusing them, the team builds each layer directly on top of the last in one continuous process. This “monolithic” method uses temperatures low enough to avoid damaging the circuitry below, allowing the researchers to stack components more tightly and connect them far more densely.
NewsArticle: "First truly 3D chip fabbed at US foundry, features carbon nanotube transistors and RAM on a single die — future devices could have up to 1000x improvement in energy-delay product" (2025)
https://www.tomshardware.com/tech-industry/semiconductors/st...
westurner•1mo ago
> Instead of fabricating separate chips and then fusing them, the team builds each layer directly on top of the last in one continuous process. This “monolithic” method uses temperatures low enough to avoid damaging the circuitry below, allowing the researchers to stack components more tightly and connect them far more densely.
NewsArticle: "First truly 3D chip fabbed at US foundry, features carbon nanotube transistors and RAM on a single die — future devices could have up to 1000x improvement in energy-delay product" (2025) https://www.tomshardware.com/tech-industry/semiconductors/st...