We still use SRAM today. It's what level-1 cache and registers are implemented with - actual flip-flops, can be toggled with one cycle delay. Supercomputers used to make their entire main memory out of SRAM, effectively the whole thing was L1 cache.
The 486 has an on-chip cache - 8 or 16 KB of SRAM. Very large for the time.
Off-chip access to the DRAM involves wait states. The read or write is stalled until the DRAM enters the appropriate state. The 486 would also do block reads of 16 bytes at a time to fill an entire cache line. This is around the time main memory and the CPU became increasingly decoupled.
Avoiding all the complexity of managing DRAM is why hobbyists use SRAM these days. Basically: to avoid cost. Ironic!
(Now, I would have preferred a Lattice ICE40 FPGA as opposed to the Xilinx Spartan II XC2S100 FPGA, simply because the ICE40 toolchain is entirely open source (https://prjicestorm.readthedocs.io/en/latest/) but that's a very minor (less than 1%) extremely small "nitpick" -- on what should be praised and lauded as some truly great work!)
Anyway, to repeat, I absolutely love it!
Upvoted and favorited!
Well done!
Here is a prototype https://imgur.com/gallery/486-homebrew-computer-lsUiWdw
The most impressive part of this build is that maniek86 (Piotr Grzesik) is still in High School (electronics oriented CTE).
We are in sync! I also fell in love with this project after seeing it on Hackaday. At first I was just impressed, but the more I dug in (pcb, vhdl) the more I couldnt stop obsessing over it :) Its super well documented, well structured and easy to follow. True hello world of building a 386/486 chipset. My HaD comment from 3 weeks ago:
HaD blog entry doesnt do justice to this AMAZING project. Author implemented:
Intel 386/486 CPU bus handling
ISA bus handling
reused vintage 486 CPU
reused vintage 8259 PIT (timer)
reused vintage 8254 PIC (interrupts)
Want to hear something wild – this was maniek86s first 4 layer board ever :o Talk about jumping into deep water.
From reading maniek86 blog it all started when he got scammed buying Chinese no name ISA/PCI Post Code analyzer card that didnt really support ISA side https://maniek86.xyz/pl/blog.php?p=31 :
"It turned out that ISA part of the card was a scam – it could only measure voltages and show CLK, RDY, and reset signals. I was disappointed. I had to repair the motherboard without the help of POST codes. Eventually, I managed to fix it, but the card didn’t meet my expectations. That’s when I came up with the idea of building my own card instead of buying another one."
And so he did, just like Bender with blackjack and all! End result is https://maniek86.xyz/projects.php?p=41 https://github.com/maniekx86/isa_debug_post_card https://github.com/maniekx86/isa_debug_post_card_cpld_source deserving its own HaD entry. To make Post Code card maniek86 had to:
- learn how ISA bus works
- learn VHDL
- do digital archeology to dig up 17 year old Xilinx ISE that could support obsolete XC95144XL 5Volt CPLD
- learn about output buffers the hard way by frying first XC95144XL driving LEDd directly, didnt we all? :)
This Post Code analyzer card led directly to creation of M8SBC. What a hacking tour the force. I absolutely love it.
fecal_henge•2w ago
You mentioned something about custom holes. What does that mean?
blacklion•2w ago