Who: Systems engineer, 16 years in real-time embedded and media pipelines.
Why: Because "average fast" isn't good enough for robotics or hard real-time control. I needed deterministic latency — a system where the physics of the hardware guarantees the timing.
What: Decima-8 is a router-less neuromorphic architecture:
• Values are Level16 [0..15] (Tetradic/Non-binary), not float32 or binary spikes
• Weights are SignedWeight5 [-7..+7], (Lateral inhibition in hardware)
• Accumulators are signed i16 with saturating arithmetic + signed decay
• Activation is cascade-based (locked tile enables children), not packet-routed
• Cycle is fixed: READ → WRITE, 22-311µs depending on fabric size (256-4096 tiles) on i5-3550 (2012) one core
• No routers, no dynamic allocation, no data-dependent branching
Proof:
• Emulator (C++23, MIT): github.com/rulerom/decima8
• Spec (open PDF): decima.rulerom.com/en/codex/
• Benchmarks (i5-3550, single core): 256 tiles @ 22µs, 4096 tiles @ 311µs, zero jitter
• IDE (1.3MB native, offline): visual "baking" of personalities, no ML training required
Status:
• Spec + Emulator + libd8p: OPEN (MIT/Apache 2.0)
• IDE: closed binary, free to use (reference UX)
• Store: curated, PKI-signed personalities (optional for local use)
Decima-8 is not a CPU replacement. It's not "another AI". It's a deterministic reflex node for pattern recognition — where the physics of the computation guarantees the timing.
If you spot a bug in the math, a flaw in the spec, or a better way to pack 5-bit weights — I'm listening. The emulator is bit-accurate to the intended silicon, so fork away.
intentgarden•2h ago
Why: Because "average fast" isn't good enough for robotics or hard real-time control. I needed deterministic latency — a system where the physics of the hardware guarantees the timing.
What: Decima-8 is a router-less neuromorphic architecture: • Values are Level16 [0..15] (Tetradic/Non-binary), not float32 or binary spikes • Weights are SignedWeight5 [-7..+7], (Lateral inhibition in hardware) • Accumulators are signed i16 with saturating arithmetic + signed decay • Activation is cascade-based (locked tile enables children), not packet-routed • Cycle is fixed: READ → WRITE, 22-311µs depending on fabric size (256-4096 tiles) on i5-3550 (2012) one core • No routers, no dynamic allocation, no data-dependent branching
Proof: • Emulator (C++23, MIT): github.com/rulerom/decima8 • Spec (open PDF): decima.rulerom.com/en/codex/ • Benchmarks (i5-3550, single core): 256 tiles @ 22µs, 4096 tiles @ 311µs, zero jitter • IDE (1.3MB native, offline): visual "baking" of personalities, no ML training required
Status: • Spec + Emulator + libd8p: OPEN (MIT/Apache 2.0) • IDE: closed binary, free to use (reference UX) • Store: curated, PKI-signed personalities (optional for local use)
Decima-8 is not a CPU replacement. It's not "another AI". It's a deterministic reflex node for pattern recognition — where the physics of the computation guarantees the timing.
If you spot a bug in the math, a flaw in the spec, or a better way to pack 5-bit weights — I'm listening. The emulator is bit-accurate to the intended silicon, so fork away.