This is a collection of my projects, with the umbrella name of VitaOS-Libre. It includes my Open Source VitaFPGA Architecture, named Vita because my name has the word “Vita” in it (I’m “Vita”lii Skikun).
You can also run my FPGA Architecture by connecting many of the VitaFPGA Architecture Logic Blocks into a square grid array and write a pin-constraints file for the square grid array to get it to work on commercially-available FPGA chips. What I would call “The VitaFPGA Hardware Abstraction Layer.” This is an alternative to making the chips that would use my FPGA Architecture, which I might be able to do in the future by sharing a semiconductor shuttle run.
And by Halting Problem Solution, I mean “run 1 clock cycle, compare previous savestate with current savestate. Run 2 clock cycles, repeat. Run 3 clock cycles, repeat.” You check the number of loop steps and if it matches, it’s a detected infinite loop. The limit is eventually reached when the arbitrary precision integer consumes all available memory of the machine, or the number of atoms in the universe, whatever comes first. So technically, if the computer fits in this universe, then it can’t have a loop with a infinite number of steps until it repeats.
The QuantumTunnelingHWRNG idea is the idea that transistor values quantum tunnelling is teleportation faster than the speed of light, making the HWRNG 100% random. (In theory.)
Before I wrote my FPGA from scratch, I saw a entry on OpenCores.org about the Confluence Reconfigurable Computing Array. I read that it’s a square grid array, allowing for 1+ GHz. I stopped reading that after that point. My FPGA isn’t based on any of that computing array’s code, as I didn’t look at any of it. My FPGA simply got inspiration from its square grid array giving 1+ GHz idea. I also saw the OpenCores.org GPLv1 eFPGA as a project link. My code isn’t based on any of their code.
pcwir•1h ago
You can also run my FPGA Architecture by connecting many of the VitaFPGA Architecture Logic Blocks into a square grid array and write a pin-constraints file for the square grid array to get it to work on commercially-available FPGA chips. What I would call “The VitaFPGA Hardware Abstraction Layer.” This is an alternative to making the chips that would use my FPGA Architecture, which I might be able to do in the future by sharing a semiconductor shuttle run.
And by Halting Problem Solution, I mean “run 1 clock cycle, compare previous savestate with current savestate. Run 2 clock cycles, repeat. Run 3 clock cycles, repeat.” You check the number of loop steps and if it matches, it’s a detected infinite loop. The limit is eventually reached when the arbitrary precision integer consumes all available memory of the machine, or the number of atoms in the universe, whatever comes first. So technically, if the computer fits in this universe, then it can’t have a loop with a infinite number of steps until it repeats.
The QuantumTunnelingHWRNG idea is the idea that transistor values quantum tunnelling is teleportation faster than the speed of light, making the HWRNG 100% random. (In theory.)
Before I wrote my FPGA from scratch, I saw a entry on OpenCores.org about the Confluence Reconfigurable Computing Array. I read that it’s a square grid array, allowing for 1+ GHz. I stopped reading that after that point. My FPGA isn’t based on any of that computing array’s code, as I didn’t look at any of it. My FPGA simply got inspiration from its square grid array giving 1+ GHz idea. I also saw the OpenCores.org GPLv1 eFPGA as a project link. My code isn’t based on any of their code.