We need more games like this so that the younger population get some sort of exposure to the hardware side of things, before AI takes over that field. I would also think that take-home electronic and soldering kits for adults and younger folks would be another way to reduce dependance on AI.
Edit: Confirmed fixed.
Really threw me for a loop! I'm still trying to wrap my head around making level 3's NOT gate.
This is such a cool idea, definitely the first 3-state circuit puzzler I've seen! Throw a cute story over it and I bet this would get some takers on Steam.
Well done and keep it up :)
otherwise, looks polished and fills in a nice niche!
That said, I'm not sure how useful expanding most of the acronyms would be. Names like Negative/Positive Metal Oxide Semiconductor aren't exactly self-explanatory, Vdd isn't really an acronym, etc..
One note: It isn't immediately obvious that the In/Out nodes can be connected to multiple wires, made the first few rounds harder to work thru.
Some comments:
- I didn't like the "truth tables" one, I got many duplicate questions and for some reason I got only one second for the first question. The rest of the questions I managed to answer correctly but I still got only one start out of three?
- I got very confused by the capacitor. Capacitors do not have an "enable" gate! In fact, in 2.7 (1T1C) you are supposed to build the enable gate -- with a transistor. So currently, you can just simply not build the enable gate and use the one already in the primitive, meaning you don't need the NMOS gate at all.
Was this made using LLM-assistence? (Not judging, I'm just interested!) I'd love to hear more about your workflow and how you managed to produce a good UI as it's something I couldn't do if my life depended on it, and it's a skill I'd like to learn.
Ill fix the truth tables bug (i think i know the issue), the stars come from playing in endless mode
I used claude quite a bit, it struggled through a lot of this (wiring and simulation systems in particular), but managed to crank this out, for the graphics i was extremely detailed in terms of what i wanted i'd say
On the capacitor though, the capacitor level is weird as you don't build the capacitor charge system with transistors. Though I definitely get that the simulation engine is for digital stuff, not analog :)
Also a general feedback on the time-based challenges: dial them back. A lot. Most of them are just not interesting and have zero learning value. In fact, the "DRAM refresh" one just made me quit the game (clicking on 8 rows to keep them fresh). Okay, 10s is enough, I got the point. No need to hold up for a whole minute. Kinda same for the hex one. However, some of them are good, and the UI for the binary ones is great, especially for the two's complement one!
Small nitpick on the UI: some blocks don't have their connections aligned with the grid, making the wiring OCD-incompatible. But that's minor. It's a shame since the wire routing algorithm works quite well overall, and I'm impressed an LLM could produce that good of an UI!
Otherwise, quite a fun little game, if slow paced when one already knows some bits of digital logic. Keep up!
Thanks, I appreciate all the feedback, fixes coming in the next push
I would think that if you wanted to make it so that the storage element was connected either for reading or for writing by the WL and otherwise disconnected, you would need two transistors, not just one.
Perhaps this was meant to say "for writing either a 0 or a 1"?
If someone is seeing this for the first time they may have never seen some of those gates and you quiz them.
Then finally after passing the quiz, you define NAND and NOR and Inverter.
Swap the teaching one to be the intro to the truth tables one.
Second bit of feedback is the timer. Increase the time allotted. I know them very well and still was struggling to get all the input correct before the timer hit. Or consider possibly just eliminating the timer completely - if your goal is to be sure that they know them.
* Sometimes explanations are overly lacking, other times they get repetitive. This feels like it needs to be accompanied by a course to fully deliver value. For instance, we're kind of thrown into truth gates without having really gone over them. And understanding how to combine NMOS and PMOS gates could use a better intro. Once I knew the answers, I got my brain to reset to my VLSI course from college, but I think a better primer could've accomplished that. In other places, I feel like we get more refreshers on some components than others.
* The routing algorithm needs to be better. I get a lot of staircase wires and straight up overlaps.
* Right clicking should clear attempted connections.
* There should be away to delete components you've placed. Maybe I just couldn't figure it out.
* I think icons should be included on the components pane. I kept clicking NOR when I wanted NOT and a better visual cue would have helped.
* It feels like difficulty is all over the place. Perhaps this is corrected with better explanations, but creating the NAND gates and NOR gates were much more difficult compared to AND and OR. Perhaps actually having us construct those gates without NOT would change the difficulty curve.
* The success overlay shows up too fast. Especially on levels that are just a demonstration (like the NMOS and PMOS Again levels) you don't get to to see everything the level is trying to demonstrate before the level announces that you have succeeded.
* In the intros, when there are new components, their description pops in. Instead, it should just advance like a slide. It's very jarring.
* Also, it's unclear that those aren't part of the intro. Maybe instead of popping them up, flash the little information icon next to them.
* What you call a capacitor I believe is actually a combination of a transistor and a capacitor. I think people will be hard pressed to find documentation on a capacitor with an enable switch. But, then you use this same capacitor to form a 1T1C cell. I'm rather confused.
* Many times when I finished a level, the circuit would switch to a prior level's solution.
* Some components have the same letters for every terminal (e.g. half-adders), meaning you need to scroll over the terminals to know what they do.
* Some levels have many test cases, and there's now way to see them all.
* Level 2.3 talks about us having registers, but we never covered those. In fact, I think we're still a ways away since we need to get from switches to flip-flops then to registers.
There isn't much order to this. Just what I recorded while working through it. Overall it's pretty good, I just think polish would got quite a ways.
Thank you for sharing this! I'm really excited to get to the more GPU specific parts. I basically did this for CPUs in college and I'm excited to see what preconception and missing conceptions I have for GPUs.
I'll be uploading arcs 3 and 4 soon (which will be programming the CPU and the start of GPU arch soon (people have gone through arcs 1 and 2 slightly faster than I expected)
> Wire an NMOS transistor so that when In is 1, the output is pulled to ground (0). When In is 0, the output should be unconnected (Z).
Certainly:
(a) The nMOS has 3 connections: its drain is only connected to the output (no +Vdd supply), it's source is tied to ground, it's gate is tied to the signal input
(b) When the gate (input) is driven high, the nMOS transistor turns "on," connecting the output to the source (which is grounded). This acts as a "pull-down network"
(c) When the gate is driven low, the nMOS turns "off," leaving no connection to the output. This is equivalent to a "high-impedance" / "unconnected" / "Z" output
Fails 1/2 tests
(Edit) - I thought the light grey, thick line on the background grid was a wire from "input" to the transistor's gate. It is not. You need to explicitly add a wire from "input" to gate :\
If I could make a recommendation, get rid of the grid lines entirely and only have 'dots' at regular spacing. Here's what Cadence Virtuoso looks like (the most popular circuit schematic tool for integrated circuit design):
https://www.eecs.umich.edu/courses/eecs311/f09/tutorials/cad...
Wire an NMOS transistor so that when In is 1, the output is pulled to ground (0). When In is 0, the output should be unconnected (Z).
The way it's worded it sounds like you need 'an NMOS' ie a single one? So I messed around but then I remembered seeing gates made from two transistors in my dusty memory.
(edit) I see there _is_ a one transistor solution... I'm pretty sure I tried that though. :/
also lmfao bikeshedding a custom language is EXACTLY what i would expect from the dev of that kinda nerd game. feels like a good sign tbh
I don't see any button labeled that
Ive added this to the HN Arcade! https://hnarcade.com/games/games/mvidia
also it kept showing the same table to me like 4 times
- Made timed minigames optional (e.g. binary tables)
- Added 7 (optional) intro levels to walk through pmos and nmos transistors
- Fixed the bug in the capacitor levels
- Changed editor bg to use dots instead of lines to fix wire confusion
G0 = D0 AND SEL
G1 = NOT SEL
G2 = D1 AND G1
G0 -> Ans
G2 -> Ans
For the PMOS, the output toggles between 1 and 0 (opposite the gate) as expected. However, for the NMOS, the output is always 0.
I don't understand why GND pulls VDD down to 0 for the NMOS, but not the PMOS.
I didn't actually finish Act 2, but it seems to end in a conventional processor with the GPU first coming after another two acts currently under construction.
If anybody can create something similarly interactive, educational and hands-on for microbiology or robotics, I am happy to sponsor your cost.
Im a software dev, so not that much hardware experience
Thank you for the game by the way! It's nice to recall my asic classes, and looking forward to GPU specific chapters.
For level 1.1 the solution is basically to take the ground and use that as a singular input to the source pin of an nmos transistor, let the input to the level be the gate pin of that same nmos transistor, and to let the drain (top) pin of that nmos transistor connect to the level's output
Teaching is challenging stuff. You have to step out of your current mindset and think with the mind of someone that sees this stuff for the first time. It is not easy to make things look easy and simple. Specifically, I think you need a lot more exploration about cmos logic, about how one side pulls the output up or the other side pulls the output down but they are never on at the same time, about how they effectively amplify the result so the output does not have to depend on the power of the input, etc. Perhaps you can try to have people design things in NMOS logic than in PMOS logic and then combine the two to make a CMOS design to see how they complement each other.
But I do not want to discourage you. This is a very promising start and you should continue if you have the time.
Also, the timed answers -- are you kidding me? The time is waaay too short. And you fail all if you fail a single answer. Oh what is 0xDE in decimal, all I have to do is multiply 16 by 13 and add 14 to that. In my head in 12 seconds. Also the time is not sufficient for filling out truth tables, especially with a laptop trackpad. I was able to pass the truth tables, but gave up on hexracing.
Ok and here are some more specific issues.
-The wires seem to snap in position in a way that they superimpose each other so it becomes very difficult to see what your circuit is doing.
- truth tables seem to be bugged. If you have more inputs than the gate whose truth table you are looking at, sometimes it will generate a fictitious truth table with extra inputs. Thus, some times i get a NOT truth table that has two inputs.
- the ground element should have its connection circle on the top, not the bottom. I realized that you can rotate by pressing R, but the site does not mention that anywhere.
I intentionally made it s.t the truth tables are based on not just the input into the node, but based on all actual inputs to the node (so if you have additional processing on input x and y, itll show you the not w/ respect to input x and y and not just the immediate input).
will add a rotating cue in the next update
- Nice idea, though after playing Turing complete, I would like to skip the beginning and move to stuff that makes GPUs different to CPUs. But it's understandable.
- I'm not smart enough to intuit NAND from transistors. I'm also not sure I will be alone in that. It's such a weird difficulty wall.
- Speaking of, the difficulty is all over the place. Though easy mode is appreciated.
- Even with a n key rollover keyboard, I couldn't complete the capacitor refresh level. It seems like it speeds up and certain capacitors already start empty.
- The routing for wires is no good atrocious. Any level with more than 8 components will end up impossible to read.
- It doesn't help that you can't color code or even path wires manually.
- Might be Firefox only, but I had a hard time selecting the connection points.
- Dragging the mouse along the edge should pan. Otherwise you have to drop the connection and zoom.
- I appreciate the added "show solution". But it's not really giving you a solution. It's just a better hint.
- An option to show all tests or at least more tests would get great.
I agree with you, because I feel like I only got that one because I happened to get curious about CMOS (PMOS + NMOS) logic earlier this year, and remembered the general idea from before. Otherwise, I don't think I would have figured that out either. Google image search for CMOS NAND basically shows the solution, but the game doesn't tell you that's what it is until after you beat the level. I think seeing the answer, then immediate trying to reproduce it from memory is a good way to learn. Then if you try again the next day/week/month and are still able to remember it, then you've learned it.
I also looked up a solution for the full adder since I couldn't quite remember how it worked.
Tangentially, I've gone through similar material over time repeatedly in the games nandgame and Turing Complete, going through the Nand 2 Tetris course (on Coursera), building Ben Eater's breadboard 8-bit computer, reading "Code" by Charles Petzold and "The Pattern on the Stone" by Danny Hillis and "Digital Computer Electronics" by Malvino since that was what Ben Eater partly based his computer design on, and going over digital logic in CS-related EE courses up through how a CPU is made. But most of those barely cover anything below the logic gate level and I don't think any of them covered CMOS/NMOS/PMOS specifically which is why I got curious about them this year.
It's pretty fun though (my type of fun anyway), and I'm really curious to see how the rest of it goes since it's building a GPU instead of a CPU for a change.
I see a difficulty pop up after I click "run tests" but it then gets hidden and doesn't do anything.
This was after selecting intermediate on the truth tables level, then clicking "next level" from there.
Also when you give a solution, you probably need an explanation of why that works.
Can't wait till you add the additional coming soon levels.
Your feedback feature seems broken. I tried giving feedback about some basic bugs and it kept saying can't send message.
Please also add a waitlist to notify when you release the additional levels.
NANDgame ( Free! https://nandgame.com/ )
Silicon Zeroes ( https://store.steampowered.com/app/684270/Silicon_Zeroes/ )
Turing Complete ( https://store.steampowered.com/app/1444480/Turing_Complete/ )
Human Resource Machine / 7 Billion Humans ( https://store.steampowered.com/app/792100/7_Billion_Humans/ )
MHRD ( https://store.steampowered.com/app/576030/MHRD/ )
Some like Human Resource Machine take the approachof
I wish Turing Complete wasn't quite so buggy or awkward, for a while it was by far the most promising of the bunch, but it's never quite polished and it's ended up in a bit of frustrating state.
Notable mention also to The Signal State, Shenzhen I/O, and TIS100 which are higher level than this, but scratch a similar itch.
there's ones like TIS100 which I keep meaning to revisit, but I find it very difficult to get back into these games without starting from scratch, and resetting my TIS100 progress is too intimidating.
Likewise, level 2.12 is a bit messed up, given you can ignore BitLineBar. I'm not sure what the intended solution was.
- for the load javascript from that page imposes on CPU. +15 °C in less than 30 seconds. Nothing on the page could justify that.
it was all reasonably easy to get until you get to the sense amplifier which has an almost complete lack of explanation of why you need the required outputs, it is "clear if already known". i.e. if you've never done any electrical engineering it makes zero sense and is not the sort of thing a software developer could ever figure out with the minimal explanation.
One thing that would make it even stronger: a brief explanation panel for each level showing what real-world GPU component the puzzle maps to. When I completed the truth tables section, I wanted to know where that pattern shows up in actual silicon.
Some suggestions: - What I miss from NAND Game is the challenge of optimizing for efficiency. You'd build a component and it would let you know if it could be built with fewer NAND gates and you'd try to simplify the circuit. For example, while I did "NAND it" with 4 transistors, I did "The dual" with 5 and given the explanation I got afterwards I could have used one less. - This definitely needs to get better on mobile - The description for the first level using BitLine and BitLineBar (I think that was the Sense Amp?) doesn't really explain what it's supposed to do and I had to deduce it from the truth table.
I wish I could get into hardware chip level jobs, I was a wiz in logic gates back in university but for jobs been primarily in systems and embedded, sure you work sometimes on rtos or fpga, but it’s another thing where your whole job is designing that! Unfortunately the jobs in hardware feels like a cult, and they expect you working on some industry specific software that you can’t do/access to unless you are in the industry to start with, kinda a catch 22 situation.
nottorp•1d ago
SilentM68•1d ago