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Warcraft III Peon Voice Notifications for Claude Code

https://github.com/tonyyont/peon-ping
295•doppp•4h ago•111 comments

Discord/Twitch/Snapchat age verification bypass

https://age-verifier.kibty.town/
709•JustSkyfall•10h ago•292 comments

65 Lines of Markdown, a Claude Code Sensation

https://tildeweb.nl/~michiel/65-lines-of-markdown-a-claude-code-sensation.html
31•roywashere•1h ago•17 comments

Using an engineering notebook

https://ntietz.com/blog/using-an-engineering-notebook/
157•evakhoury•2d ago•48 comments

“Nothing” is the secret to structuring your work

https://www.vangemert.dev/blog/nothing
256•spmvg•3d ago•89 comments

D Programming Language

https://dlang.org/
107•arcadia_leak•4h ago•82 comments

From specification to stress test: a weekend with Claude

https://www.juxt.pro/blog/from-specification-to-stress-test/
4•henrygarner•17m ago•1 comments

GLM-5: Targeting complex systems engineering and long-horizon agentic tasks

https://z.ai/blog/glm-5
366•CuriouslyC•19h ago•447 comments

Fluorite – A console-grade game engine fully integrated with Flutter

https://fluorite.game/
469•bsimpson•17h ago•268 comments

Text classification with Python 3.14's ZSTD module

https://maxhalford.github.io/blog/text-classification-zstd/
192•alexmolas•3d ago•37 comments

HeyWhatsThat

https://www.heywhatsthat.com/faq.html
32•1970-01-01•2d ago•7 comments

Kanchipuram Saris and Thinking Machines

https://altermag.com/articles/kanchipuram-saris-and-thinking-machines
149•trojanalert•5d ago•27 comments

Ireland rolls out basic income scheme for artists

https://www.reuters.com/world/ireland-rolls-out-pioneering-basic-income-scheme-artists-2026-02-10/
285•abe94•16h ago•268 comments

How to make a living as an artist

https://essays.fnnch.com/make-a-living
90•gwintrob•5h ago•43 comments

NetNewsWire Turns 23

https://netnewswire.blog/2026/02/11/netnewswire-turns.html
284•robin_reala•15h ago•69 comments

Reports of Telnet's death have been greatly exaggerated

https://www.terracenetworks.com/blog/2026-02-11-telnet-routing
100•ericpauley•13h ago•42 comments

The other Markov's inequality

https://www.ethanepperly.com/index.php/2026/01/16/the-other-markovs-inequality/
28•tzury•4d ago•1 comments

WiFi could become an invisible mass surveillance system

https://scitechdaily.com/researchers-warn-wifi-could-become-an-invisible-mass-surveillance-system/
370•mgh2•5d ago•165 comments

Deobfuscation and Analysis of Ring-1.io

https://back.engineering/blog/04/02/2026/
39•raggi•3d ago•6 comments

Covering electricity price increases from our data centers

https://www.anthropic.com/news/covering-electricity-price-increases
93•ryanhn•12h ago•51 comments

RISC-V Vector Primer

https://github.com/simplex-micro/riscv-vector-primer/blob/main/index.md
15•oxxoxoxooo•4d ago•2 comments

Clay Christensen's Milkshake Marketing (2011)

https://www.library.hbs.edu/working-knowledge/clay-christensens-milkshake-marketing
5•vismit2000•4d ago•0 comments

Claude Code is being dumbed down?

https://symmetrybreak.ing/blog/claude-code-is-being-dumbed-down/
917•WXLCKNO•15h ago•593 comments

Apple's latest attempt to launch the new Siri runs into snags

https://www.bloomberg.com/news/articles/2026-02-11/apple-s-ios-26-4-siri-update-runs-into-snags-i...
88•petethomas•13h ago•123 comments

GLM-OCR – A multimodal OCR model for complex document understanding

https://github.com/zai-org/GLM-OCR
262•ms7892•4d ago•72 comments

From 34% to 96%: The Porting Initiative Delivers – Hologram v0.7.0

https://hologram.page/blog/porting-initiative-delivers-hologram-v0-7-0
38•bartblast•9h ago•6 comments

Show HN: CodeRLM – Tree-sitter-backed code indexing for LLM agents

https://github.com/JaredStewart/coderlm/blob/main/server/REPL_to_API.md
54•jared_stewart•20h ago•17 comments

Microwave Oven Failure: Spontaneously turned on by its LED display (2024)

https://blog.stuffedcow.net/2024/06/microwave-failure-spontaneously-turns-on/
94•arm•13h ago•30 comments

Amazon Ring's lost dog ad sparks backlash amid fears of mass surveillance

https://www.theverge.com/tech/876866/ring-search-party-super-bowl-ad-online-backlash
564•jedberg•14h ago•303 comments

GPT-5 outperforms federal judges in legal reasoning experiment

https://papers.ssrn.com/sol3/papers.cfm?abstract_id=6155012
264•droidjj•9h ago•184 comments
Open in hackernews

How ZGC allocates memory for the Java heap

https://joelsiks.com/posts/zgc-heap-memory-allocation/
86•lichtenberger•9mo ago

Comments

gopalv•9mo ago
The 32x virtual memory to physical memory ratio plays into relocation and colored pointers (i.e pointers where some bits serve as flag bits).

Putting the actual data layouts in 44 bits out of 64 is a neat trick which relies on the allocator being aware of the mappings between physical and virtual addresses.

twoodfin•9mo ago
When your comment and the article refer to “physical” addresses, those are physical in the context of the JVM, right? To the OS they’re virtual addresses in the JVM process space?
acchow•9mo ago
Correct. ZGC has no way to escape from the virtualization by the kernel (assuming your hardware and kernel uses an MMU)
MBCook•9mo ago
Thank you for the answer, I was wondering that as well.
hinkley•9mo ago
In the beginning of the 32 bit revolution, when the future was here but unevenly distributed, there was a lot of talk about how 32 bit pointers would fundamentally change how people wrote code. Among other things it got rid of a bunch of odd bookkeeping, and if you don’t have to do the bookkeeping you don’t have to write the code in a way that supports it, so you can do other things.

Not too long after someone asked what sort of interesting changes 64 bit will bring. And I’ve been keeping that question in the back of my mind ever since.

Aliasing memory multiple times in order to do read or write barriers and make GC much cheaper is a pretty good one. But another one I know of is that one of the secrets of the L4 microkernel is that its IPC speed comes substantially from reducing the amount of TLB work that needs to be done to switch to another process running in a different address space. They use the same address space and only swap out the access rights which cuts the call overhead in half. It’s pretty easy to put a bunch of processes into a 64 bit address space and just throw each one a randomly located 4GB slice of RAM.

twoodfin•9mo ago
Yeah, would love to see the CPU vendors invent some primitives to let user code pull those kinds of privilege isolation tricks within a single process and address space.

Something like: “From now on, code on these pages can only access data on these pages, and only return to/call into other code through these gates…”

hinkley•9mo ago
Thread based seems like it at least should be possible.
ahartmetz•9mo ago
I've had some ideas about avoiding format validation in IPC receivers if the data is encoded by trusted code, which is also the only code that has rights to send the IPC data / to connect to the receiver. I can't really think of an important problem that it would solve, though. DBus always validates received data, but it's not really meant or very suitable for large amounts of data anyway.
twoodfin•9mo ago
What I’m looking for is a way for a process to de/re-escalate its privileges to access memory, without an expensive context switch being required at the transition. The CPU would simply enforce different rules based on (say) the high-order bits of the instruction pointer.

Imagine a server process that wants to run some elaborate third-party content parser. It’d be great to be sure that no matter how buggy or malicious that code, it can’t leak the TLS keys.

Today, high-security architectures must use process isolation to achieve this kind of architectural guarantee, but even finely tuned IPC like L4’s is an order of magnitude slower than a predictable jump.

gpderetta•9mo ago
For a brief moment Intel supported MPX which did something similar.

You can also play tricks with the virtualization hardware, bit it need kernel support.

Eventually we will get segments back again.

MarkSweep•9mo ago
That would be pretty cool. Something like the Win32 function GetWriteWatch, but implemented in hardware instead of the page fault handler (I assume).

https://learn.microsoft.com/en-us/windows/win32/api/memoryap...

Or some sort of special write barrier store op-code, idk.

mike_hearn•9mo ago
It exists, that's called MPKs.
twoodfin•9mo ago
I don’t think MPK’s will fit the need I have. Simply: Run some arbitrary, untrusted, non-sandboxed code in the same thread with assurance it can’t read page X. When that code completes and I’m back in code I trust, X is readable again.

Is that something MPK makes possible? The doc I’ve read suggests either your process can flip permission bits or it can’t. Great for avoiding out-of-sandbox reads. But if there’s arbitrary execution happening, why can’t that code flip the access to secrets back on?

mike_hearn•9mo ago
Oracle Labs has tech that does that:

https://youtu.be/T05FI93MBI8?si=EieFgujaGiW2gbO8&t=958

The trick is to do a cascading disassembly of all untrusted code you'll execute to prove it can't change the MPK register.

twoodfin•9mo ago
Wow. Neat trick and exactly the kind of thing I was looking for.

Thanks!

EDIT: Looks like this is the relevant paper from the Graal team: https://www.graalvm.org/resources/articles/binsweep.pdf

jdougan•9mo ago
Is that something like the memory protection scheme on the Newton OS?
nyanpasu64•9mo ago
Isn't not swapping page tables during a call precisely what the KPTI mitigations had to turn off for Meltdown mitigations?
pron•9mo ago
For relevant upcoming changes see Automatic Heap Sizing for ZGC: https://openjdk.org/jeps/8329758