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Xiaomi: New CPU matches Apple cores single threaded, much faster multithreaded

https://twitter.com/lemire/status/2091894299289874926
586•tosh•5h ago•394 comments

MS Paint and Photos inivisibly watermark even locally generated output with GUID

https://xusheng.dev/posts/reversing/mspaint_invisible_watermark/main/
418•ComputerGuru•5h ago•161 comments

The entire city of San Francisco as a video game

https://sf.thijs.gg/
213•centrosphere•3h ago•79 comments

IPFS Maintainers Winding Down

https://ipshipyard.com/blog/2026-the-end-of-ipfs-at-shipyard/
271•iand•5h ago•136 comments

Oceans hit highest temperature on record

https://www.bbc.com/news/articles/c62m4gpnp78o
194•tcp_handshaker•1h ago•73 comments

A Claude Code skill that recovers export-blocked Kindle highlights

https://github.com/l3a0/claude-plugins
35•l3a0•1h ago•5 comments

How Europe is killing makers and micro-entrepreneurs

https://lectronz.com/u/lectronz/articles/how-europe-is-killing-makers-and-micro-entrepreneurs
888•l-one-lone•7h ago•583 comments

Jabber/XMPP: 25 Years of Digital Independence

https://gultsch.de/posts/25-years-of-digital-independence/
109•inputmice•5h ago•41 comments

LLMs could control their host machines by exploiting inference engines

https://boydkane.com/essays/llms-could-control-their-host-machines-by-exploiting-inference-engines
42•zdw•2h ago•16 comments

Anger, Anxiety and Agency

https://lucumr.pocoo.org/2026/8/24/anger-anxiety-agency/
51•lumpa•2h ago•61 comments

OpenAI: GPT 5.6 Sol price reduction (until at least Nov 21)

https://developers.openai.com/api/docs/pricing
240•tosh•5h ago•213 comments

Autostep (YC P26) Is Hiring AI/Fullstack Engineers and a Chief of Staff

https://app.dover.com/Autostep/careers/e9510e3b-a854-4e48-9e5d-c89796acaed4
1•adawg4•3h ago

Where did all the public bathrooms go?

https://daily.jstor.org/where-did-all-the-public-bathrooms-go/
58•herbertl•3h ago•98 comments

Show HN: PicoMQ – Durable Streams over HTTP, on object storage

https://picomq.com/
59•adesh_nalpet•4h ago•9 comments

Hot Chips 2026: CUDA Targets RISC-V – By Chester Lam

https://chipsandcheese.com/p/hot-chips-2026-cuda-targets-risc
54•rbanffy•4h ago•7 comments

I were 17, I'd learn how to build LLMs from scratch

https://twitter.com/paulg/status/2091544343589060625
475•bilsbie•1d ago•566 comments

SeL4 security proofs now complete on AArch64

https://proofcraft.systems/news-2026/#2026-08-21
152•snvzz•9h ago•34 comments

Show HN: Kern – container and resource runtime in a 1.5 MB binary, no daemon

https://github.com/getkern/kern
29•realexweb•2h ago•4 comments

Removed all counters, replies, following/ers, timestamps, from textlog

https://textlog.cc/post/2059
26•stagas•2h ago•11 comments

Peppermint oil reduces blood pressure by 8.48 mmHg in small study

https://journals.plos.org/plosone/article?id=10.1371/journal.pone.0344538
54•brandonb•6h ago•28 comments

Coding expertise is going to collapse from AI reliance

https://larsfaye.com/articles/ai-coding-will-prevent-expertise
340•larsfaye•5h ago•361 comments

What Is a Syslog Server?

https://blog.greencloudvps.com/what-is-a-syslog-server.php
28•theanonymousone•2h ago•15 comments

The "File" menu isn't about files

https://adam.farkas.pro/your-file-menu-isnt-about-files/
31•b__d•2h ago•46 comments

Executable Is a SQLite Database

https://fzakaria.com/2026/08/23/your-executable-is-a-sqlite-database
436•setheron•16h ago•88 comments

Show HN: A techno machine in one HTML file, with verifiable renders

https://ssx360.github.io/rack-02/?src=hn
129•ssx360•7h ago•23 comments

Octopus intelligence may be related to never-before-seen mutation

https://www.smithsonianmag.com/smart-news/why-are-some-octopuses-so-smart-the-answer-might-lie-in...
17•bookofjoe•3h ago•6 comments

Codefloe Is a Professionally Hosted Public Git Forge

https://codefloe.com/
38•jeremyjh•6h ago•14 comments

FDA clears blood test to aid evaluation for Alzheimer's disease

https://medicine.washu.edu/news/fda-clears-blood-test-to-aid-evaluation-for-alzheimers-disease/
167•dabinat•14h ago•82 comments

Show HN: GlassBox – what the browser reveals, and how identifiable you are

https://glassbox.codecanary.org
70•tke248•4h ago•36 comments

Could We Dredge the Netherlands Without Fossil Fuels? (2018)

https://solar.lowtechmagazine.com/2018/08/could-we-dredge-the-netherlands-without-fossil-fuels
36•at1as•5h ago•39 comments
Open in hackernews

How ZGC allocates memory for the Java heap

https://joelsiks.com/posts/zgc-heap-memory-allocation/
86•lichtenberger•1y ago

Comments

gopalv•1y ago
The 32x virtual memory to physical memory ratio plays into relocation and colored pointers (i.e pointers where some bits serve as flag bits).

Putting the actual data layouts in 44 bits out of 64 is a neat trick which relies on the allocator being aware of the mappings between physical and virtual addresses.

twoodfin•1y ago
When your comment and the article refer to “physical” addresses, those are physical in the context of the JVM, right? To the OS they’re virtual addresses in the JVM process space?
acchow•1y ago
Correct. ZGC has no way to escape from the virtualization by the kernel (assuming your hardware and kernel uses an MMU)
MBCook•1y ago
Thank you for the answer, I was wondering that as well.
hinkley•1y ago
In the beginning of the 32 bit revolution, when the future was here but unevenly distributed, there was a lot of talk about how 32 bit pointers would fundamentally change how people wrote code. Among other things it got rid of a bunch of odd bookkeeping, and if you don’t have to do the bookkeeping you don’t have to write the code in a way that supports it, so you can do other things.

Not too long after someone asked what sort of interesting changes 64 bit will bring. And I’ve been keeping that question in the back of my mind ever since.

Aliasing memory multiple times in order to do read or write barriers and make GC much cheaper is a pretty good one. But another one I know of is that one of the secrets of the L4 microkernel is that its IPC speed comes substantially from reducing the amount of TLB work that needs to be done to switch to another process running in a different address space. They use the same address space and only swap out the access rights which cuts the call overhead in half. It’s pretty easy to put a bunch of processes into a 64 bit address space and just throw each one a randomly located 4GB slice of RAM.

twoodfin•1y ago
Yeah, would love to see the CPU vendors invent some primitives to let user code pull those kinds of privilege isolation tricks within a single process and address space.

Something like: “From now on, code on these pages can only access data on these pages, and only return to/call into other code through these gates…”

hinkley•1y ago
Thread based seems like it at least should be possible.
ahartmetz•1y ago
I've had some ideas about avoiding format validation in IPC receivers if the data is encoded by trusted code, which is also the only code that has rights to send the IPC data / to connect to the receiver. I can't really think of an important problem that it would solve, though. DBus always validates received data, but it's not really meant or very suitable for large amounts of data anyway.
pron•1y ago
For relevant upcoming changes see Automatic Heap Sizing for ZGC: https://openjdk.org/jeps/8329758
twoodfin•1y ago
What I’m looking for is a way for a process to de/re-escalate its privileges to access memory, without an expensive context switch being required at the transition. The CPU would simply enforce different rules based on (say) the high-order bits of the instruction pointer.

Imagine a server process that wants to run some elaborate third-party content parser. It’d be great to be sure that no matter how buggy or malicious that code, it can’t leak the TLS keys.

Today, high-security architectures must use process isolation to achieve this kind of architectural guarantee, but even finely tuned IPC like L4’s is an order of magnitude slower than a predictable jump.

gpderetta•1y ago
For a brief moment Intel supported MPX which did something similar.

You can also play tricks with the virtualization hardware, bit it need kernel support.

Eventually we will get segments back again.

MarkSweep•1y ago
That would be pretty cool. Something like the Win32 function GetWriteWatch, but implemented in hardware instead of the page fault handler (I assume).

https://learn.microsoft.com/en-us/windows/win32/api/memoryap...

Or some sort of special write barrier store op-code, idk.

mike_hearn•1y ago
It exists, that's called MPKs.
twoodfin•1y ago
I don’t think MPK’s will fit the need I have. Simply: Run some arbitrary, untrusted, non-sandboxed code in the same thread with assurance it can’t read page X. When that code completes and I’m back in code I trust, X is readable again.

Is that something MPK makes possible? The doc I’ve read suggests either your process can flip permission bits or it can’t. Great for avoiding out-of-sandbox reads. But if there’s arbitrary execution happening, why can’t that code flip the access to secrets back on?

mike_hearn•1y ago
Oracle Labs has tech that does that:

https://youtu.be/T05FI93MBI8?si=EieFgujaGiW2gbO8&t=958

The trick is to do a cascading disassembly of all untrusted code you'll execute to prove it can't change the MPK register.

twoodfin•1y ago
Wow. Neat trick and exactly the kind of thing I was looking for.

Thanks!

EDIT: Looks like this is the relevant paper from the Graal team: https://www.graalvm.org/resources/articles/binsweep.pdf

jdougan•1y ago
Is that something like the memory protection scheme on the Newton OS?
nyanpasu64•1y ago
Isn't not swapping page tables during a call precisely what the KPTI mitigations had to turn off for Meltdown mitigations?