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Noise infusion banned from statistical products published by Census Bureau

https://desfontain.es/blog/banning-noise.html
740•nl•12h ago•467 comments

GLM 5.2 Is Out

https://twitter.com/jietang/status/2065784751345287314
369•aloknnikhil•10h ago•209 comments

Every Frame Perfect

https://tonsky.me/blog/every-frame-perfect/
577•ravenical•14h ago•189 comments

Pyodide 314.0: Python packages can now publish WebAssembly wheels to PyPI

https://blog.pyodide.org/posts/314-release/
85•agriyakhetarpal•4d ago•16 comments

Treating pancreatic tumours may have revealed cancer's master switch

https://economist.com/science-and-technology/2026/06/12/treating-pancreatic-tumours-may-have-reve...
305•andsoitis•12h ago•108 comments

FreeOberon – Open-Source, Cross-Platform, Free Pascal/Turbo Pascal-Like Language

https://github.com/kekcleader/FreeOberon
24•peter_d_sherman•2d ago•7 comments

10th Gen Honda Civic Updates Are Signed with AOSP Test Keys

https://juniperspring.org/posts/honda-evil-valet/
19•librick•1h ago•1 comments

'Tell Him He's a Piece of Shit': Meta's New AI Unit Is a Total Mess

https://www.wired.com/story/mark-zuckerberg-meta-employee-meeting-interrupt-ai/
35•momentmaker•1h ago•20 comments

ReactOS (FOSS "Windows") achieves 3D-accelerated Half-Life on real hardware

https://www.phoronix.com/news/ReactOS-Running-Half-Life
99•jeditobe•3h ago•12 comments

4 things to know about the new sunscreen ingredient the FDA approved

https://www.npr.org/2026/06/13/nx-s1-5856385/sunscreen-skin-protection-bemotrizinol
34•mikhael•1h ago•2 comments

Running DOS on Behringers DDX3216 with a DIY x86-Bios from Scratch

https://chrisdevblog.com/2026/06/08/running-dos-on-behringers-ddx3216-using-a-diy-x86-bios/
78•rasz•7h ago•17 comments

Amazon CEO's talks with U.S. officials triggered crackdown on Anthropic models

https://www.wsj.com/tech/ai/amazon-ceos-talks-with-u-s-officials-triggered-crackdown-on-anthropic...
553•ls612•9h ago•405 comments

Codex for open source

https://openai.com/form/codex-for-oss/
176•EvgeniyZh•2d ago•51 comments

GameBoy Workboy

https://tcrf.net/Workboy
161•tosh•8h ago•54 comments

A whale necropolis has been found

https://www.nature.com/articles/d41586-026-01581-x
14•tigerlily•3d ago•1 comments

Police officer investigated for using AI to 'create evidence' in multiple cases

https://news.sky.com/story/derbyshire-police-officer-investigated-for-using-ai-to-create-evidence...
239•austinallegro•6h ago•106 comments

Ancient genome duplications laid the foundations of complex brains

https://www.ox.ac.uk/news/2026-06-09-ancient-genome-duplications-laid-the-foundations-of-complex-...
17•hhs•3h ago•1 comments

A low-carbon computing platform from your retired phones

https://research.google/blog/a-low-carbon-computing-platform-from-your-retired-phones/
251•vikas-sharma•16h ago•134 comments

Appreciating Exif

https://brentfitzgerald.com/posts/appreciating-exif/
133•burnto•4d ago•29 comments

Resurrecting a soaked, corroded, and damaged Commodore SX‑64 (2025)

https://jerrylparker.com/blogs/posts/sx-64.html
20•hggh•2d ago•3 comments

Human Routers of Machine Words

https://borretti.me/article/human-routers-of-machine-words
30•zx321•4h ago•15 comments

The adder at the heart of Intel's 8087 floating-point chip

https://www.righto.com/2026/06/intel-8087-adder-reverse-engineered.html
93•pwg•9h ago•25 comments

The experience of rendering Arabic typography and its technical debt

https://lr0.org/blog/p/arabic/
195•bookofjoe•13h ago•46 comments

RTX 5080 and RTX 3090 Setup: 80 Tok/s on Qwen 3.6 27B Q8

https://imil.net/blog/posts/2026/rtx-5080-+-rtx-3090-setup-80+-tok-s-on-qwen-3.6-27b-q8/
195•iMil•16h ago•68 comments

Orthodox C++ (2016)

https://bkaradzic.github.io/posts/orthodoxc++/
85•signa11•12h ago•145 comments

AI coding at home without going broke

https://stephen.bochinski.dev/blog/2026/06/13/ai-coding-at-home-without-going-broke/
238•sbochins•9h ago•214 comments

AI OSS tool repo goes archived over night after raising $7.3M Seed

https://github.com/tensorzero/tensorzero
244•hek2sch•14h ago•159 comments

State Attorneys General Are Investigating OpenAI

https://www.nytimes.com/2026/06/13/technology/states-investigating-openai.html
35•donohoe•2h ago•3 comments

Israeli firm BlackCore suspected of meddling in New York and Scotland votes

https://www.reuters.com/world/israeli-firm-blackcore-also-suspected-meddling-nyc-scotland-votes-f...
572•pera•18h ago•331 comments

The state of building user interfaces in Rust

https://areweguiyet.com/#ecosystem
176•mahirsaid•3d ago•117 comments
Open in hackernews

How ZGC allocates memory for the Java heap

https://joelsiks.com/posts/zgc-heap-memory-allocation/
86•lichtenberger•1y ago

Comments

gopalv•1y ago
The 32x virtual memory to physical memory ratio plays into relocation and colored pointers (i.e pointers where some bits serve as flag bits).

Putting the actual data layouts in 44 bits out of 64 is a neat trick which relies on the allocator being aware of the mappings between physical and virtual addresses.

twoodfin•1y ago
When your comment and the article refer to “physical” addresses, those are physical in the context of the JVM, right? To the OS they’re virtual addresses in the JVM process space?
acchow•1y ago
Correct. ZGC has no way to escape from the virtualization by the kernel (assuming your hardware and kernel uses an MMU)
MBCook•1y ago
Thank you for the answer, I was wondering that as well.
hinkley•1y ago
In the beginning of the 32 bit revolution, when the future was here but unevenly distributed, there was a lot of talk about how 32 bit pointers would fundamentally change how people wrote code. Among other things it got rid of a bunch of odd bookkeeping, and if you don’t have to do the bookkeeping you don’t have to write the code in a way that supports it, so you can do other things.

Not too long after someone asked what sort of interesting changes 64 bit will bring. And I’ve been keeping that question in the back of my mind ever since.

Aliasing memory multiple times in order to do read or write barriers and make GC much cheaper is a pretty good one. But another one I know of is that one of the secrets of the L4 microkernel is that its IPC speed comes substantially from reducing the amount of TLB work that needs to be done to switch to another process running in a different address space. They use the same address space and only swap out the access rights which cuts the call overhead in half. It’s pretty easy to put a bunch of processes into a 64 bit address space and just throw each one a randomly located 4GB slice of RAM.

twoodfin•1y ago
Yeah, would love to see the CPU vendors invent some primitives to let user code pull those kinds of privilege isolation tricks within a single process and address space.

Something like: “From now on, code on these pages can only access data on these pages, and only return to/call into other code through these gates…”

hinkley•1y ago
Thread based seems like it at least should be possible.
ahartmetz•1y ago
I've had some ideas about avoiding format validation in IPC receivers if the data is encoded by trusted code, which is also the only code that has rights to send the IPC data / to connect to the receiver. I can't really think of an important problem that it would solve, though. DBus always validates received data, but it's not really meant or very suitable for large amounts of data anyway.
pron•1y ago
For relevant upcoming changes see Automatic Heap Sizing for ZGC: https://openjdk.org/jeps/8329758
twoodfin•1y ago
What I’m looking for is a way for a process to de/re-escalate its privileges to access memory, without an expensive context switch being required at the transition. The CPU would simply enforce different rules based on (say) the high-order bits of the instruction pointer.

Imagine a server process that wants to run some elaborate third-party content parser. It’d be great to be sure that no matter how buggy or malicious that code, it can’t leak the TLS keys.

Today, high-security architectures must use process isolation to achieve this kind of architectural guarantee, but even finely tuned IPC like L4’s is an order of magnitude slower than a predictable jump.

gpderetta•1y ago
For a brief moment Intel supported MPX which did something similar.

You can also play tricks with the virtualization hardware, bit it need kernel support.

Eventually we will get segments back again.

MarkSweep•1y ago
That would be pretty cool. Something like the Win32 function GetWriteWatch, but implemented in hardware instead of the page fault handler (I assume).

https://learn.microsoft.com/en-us/windows/win32/api/memoryap...

Or some sort of special write barrier store op-code, idk.

mike_hearn•1y ago
It exists, that's called MPKs.
twoodfin•1y ago
I don’t think MPK’s will fit the need I have. Simply: Run some arbitrary, untrusted, non-sandboxed code in the same thread with assurance it can’t read page X. When that code completes and I’m back in code I trust, X is readable again.

Is that something MPK makes possible? The doc I’ve read suggests either your process can flip permission bits or it can’t. Great for avoiding out-of-sandbox reads. But if there’s arbitrary execution happening, why can’t that code flip the access to secrets back on?

mike_hearn•1y ago
Oracle Labs has tech that does that:

https://youtu.be/T05FI93MBI8?si=EieFgujaGiW2gbO8&t=958

The trick is to do a cascading disassembly of all untrusted code you'll execute to prove it can't change the MPK register.

twoodfin•1y ago
Wow. Neat trick and exactly the kind of thing I was looking for.

Thanks!

EDIT: Looks like this is the relevant paper from the Graal team: https://www.graalvm.org/resources/articles/binsweep.pdf

jdougan•1y ago
Is that something like the memory protection scheme on the Newton OS?
nyanpasu64•1y ago
Isn't not swapping page tables during a call precisely what the KPTI mitigations had to turn off for Meltdown mitigations?