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Dolphin Emulator Progress Release 2606

https://dolphin-emu.org/blog/2026/06/25/dolphin-progress-report-release-2606/
130•exploraz•2h ago•16 comments

Half-Life 2 in a Browser

https://hl2.slqnt.dev/
368•panza•7h ago•139 comments

Anthropic says Alibaba illicitly extracted Claude AI model capabilities

https://www.reuters.com/world/china/anthropic-says-alibaba-illicitly-extracted-claude-ai-model-ca...
535•htrp•17h ago•891 comments

LastPass notifies users of yet another data breach

https://9to5mac.com/2026/06/23/lastpass-notifies-users-of-yet-another-data-breach/
105•mooreds•2h ago•49 comments

OpenAI unveils its first custom chip, built by Broadcom

https://techcrunch.com/2026/06/24/openai-unveils-its-first-custom-chip-built-by-broadcom/
738•jamdesk•19h ago•425 comments

Bohemia Interactive: Cold War Assault Remastered Source Code on GitHub

https://github.com/BohemiaInteractive/CWR
120•dewey•2d ago•24 comments

Cloudflare launched self-managed OAuth for all

https://blog.cloudflare.com/oauth-for-all/
233•terryds•10h ago•99 comments

Blogging can just be stating the obvious

https://blog.jim-nielsen.com/2026/blogging-stating-the-obvious/
297•Curiositry•13h ago•99 comments

LuaJIT 3.0 proposed syntax extensions

https://github.com/LuaJIT/LuaJIT/issues/1475
179•phreddypharkus•12h ago•102 comments

Wikipedia Workers in Britain set global first by seeking union recognition

https://utaw.tech/news/wikipedia-recognition
122•chobeat•6h ago•134 comments

45°C cooling design cuts data center water use to near zero

https://blogs.nvidia.com/blog/liquid-cooling-ai-factories/
383•nitin_flanker•22h ago•287 comments

Puzzling Success of Overparameterization: Lottery Tickets or Escape Dimensions?

https://infoscience.epfl.ch/entities/publication/9a49779b-f9f8-448d-b3d1-737c78455309
5•rbanffy•1d ago•0 comments

Medical students are using popular research tool to pump out misleading studies

https://www.science.org/content/article/medical-students-are-using-popular-research-tool-pump-out...
85•rndsignals•10h ago•44 comments

GLM-5.2 is a step change for open agents

https://www.interconnects.ai/p/glm-52-is-the-step-change-for-open
273•vantareed•2d ago•167 comments

Words, Words, Words

https://aeon.co/essays/literature-fans-should-welcome-ai-as-a-fellow-wordsmith
18•benbreen•2d ago•8 comments

Show HN: StartupsBR – A map of Brazilian startups

https://www.startupsbr.com/sao-paulo
30•leonagano•5d ago•13 comments

Dostoyevsky isn't difficult

https://www.autodidacts.io/dostoyevsky-isnt-difficult/
170•surprisetalk•2d ago•204 comments

Lies, Damn Lies and Database Benchmarks

https://questdb.com/blog/lies-damn-lies-and-database-benchmarks/
24•eigenBasis•2d ago•6 comments

RubyLLM: A Ruby framework for all major AI providers

https://rubyllm.com/
408•doener•22h ago•70 comments

Markdy: Like Mermaid Diagrams, but for Motion

https://markdy.com
94•surprisetalk•1d ago•50 comments

Qualcomm to Acquire Modular

https://www.reuters.com/business/qualcomm-buy-ai-startup-modular-2026-06-24/
211•timmyd•23h ago•78 comments

PR spam today looks like email spam in the early 2000s

https://www.greptile.com/blog/prs-on-openclaw
236•dakshgupta•22h ago•137 comments

The Xteink X4 E-Ink Reader

https://blog.omgmog.net/post/xteink-x4-e-ink-reader/
279•felixdoerp•20h ago•159 comments

Show HN: Nimic – Pure Python as a systems language with AOT compilation

https://github.com/dima-quant/nimic
23•dima-quant•1d ago•21 comments

Computer use in Gemini 3.5 Flash

https://blog.google/innovation-and-ai/models-and-research/gemini-models/introducing-computer-use-...
229•swolpers•19h ago•148 comments

Show HN: Write SaaS apps where users control where their data is stored

https://github.com/wolfoo2931/linkedrecords/
59•WolfOliver•6d ago•29 comments

Mixing Visual and Textual Code

https://arxiv.org/abs/2603.15855
56•doppioandante•11h ago•33 comments

Matt's Script Archive: The Scripts That Reshaped the Web

https://tedium.co/2026/06/22/matts-script-archive-retrospective/
68•1317•2d ago•18 comments

A Practical Guide to SSH Tunnels: Local and Remote Port Forwarding

https://labs.iximiuz.com/tutorials/ssh-tunnels
354•signa11•5d ago•66 comments

You didn't vibe code it, you stole it from open source&enterprise-licensed code

https://twitter.com/mfts0/status/2070080422482977095
10•mmunj•39m ago•0 comments
Open in hackernews

How ZGC allocates memory for the Java heap

https://joelsiks.com/posts/zgc-heap-memory-allocation/
86•lichtenberger•1y ago

Comments

gopalv•1y ago
The 32x virtual memory to physical memory ratio plays into relocation and colored pointers (i.e pointers where some bits serve as flag bits).

Putting the actual data layouts in 44 bits out of 64 is a neat trick which relies on the allocator being aware of the mappings between physical and virtual addresses.

twoodfin•1y ago
When your comment and the article refer to “physical” addresses, those are physical in the context of the JVM, right? To the OS they’re virtual addresses in the JVM process space?
acchow•1y ago
Correct. ZGC has no way to escape from the virtualization by the kernel (assuming your hardware and kernel uses an MMU)
MBCook•1y ago
Thank you for the answer, I was wondering that as well.
hinkley•1y ago
In the beginning of the 32 bit revolution, when the future was here but unevenly distributed, there was a lot of talk about how 32 bit pointers would fundamentally change how people wrote code. Among other things it got rid of a bunch of odd bookkeeping, and if you don’t have to do the bookkeeping you don’t have to write the code in a way that supports it, so you can do other things.

Not too long after someone asked what sort of interesting changes 64 bit will bring. And I’ve been keeping that question in the back of my mind ever since.

Aliasing memory multiple times in order to do read or write barriers and make GC much cheaper is a pretty good one. But another one I know of is that one of the secrets of the L4 microkernel is that its IPC speed comes substantially from reducing the amount of TLB work that needs to be done to switch to another process running in a different address space. They use the same address space and only swap out the access rights which cuts the call overhead in half. It’s pretty easy to put a bunch of processes into a 64 bit address space and just throw each one a randomly located 4GB slice of RAM.

twoodfin•1y ago
Yeah, would love to see the CPU vendors invent some primitives to let user code pull those kinds of privilege isolation tricks within a single process and address space.

Something like: “From now on, code on these pages can only access data on these pages, and only return to/call into other code through these gates…”

hinkley•1y ago
Thread based seems like it at least should be possible.
ahartmetz•1y ago
I've had some ideas about avoiding format validation in IPC receivers if the data is encoded by trusted code, which is also the only code that has rights to send the IPC data / to connect to the receiver. I can't really think of an important problem that it would solve, though. DBus always validates received data, but it's not really meant or very suitable for large amounts of data anyway.
pron•1y ago
For relevant upcoming changes see Automatic Heap Sizing for ZGC: https://openjdk.org/jeps/8329758
twoodfin•1y ago
What I’m looking for is a way for a process to de/re-escalate its privileges to access memory, without an expensive context switch being required at the transition. The CPU would simply enforce different rules based on (say) the high-order bits of the instruction pointer.

Imagine a server process that wants to run some elaborate third-party content parser. It’d be great to be sure that no matter how buggy or malicious that code, it can’t leak the TLS keys.

Today, high-security architectures must use process isolation to achieve this kind of architectural guarantee, but even finely tuned IPC like L4’s is an order of magnitude slower than a predictable jump.

gpderetta•1y ago
For a brief moment Intel supported MPX which did something similar.

You can also play tricks with the virtualization hardware, bit it need kernel support.

Eventually we will get segments back again.

MarkSweep•1y ago
That would be pretty cool. Something like the Win32 function GetWriteWatch, but implemented in hardware instead of the page fault handler (I assume).

https://learn.microsoft.com/en-us/windows/win32/api/memoryap...

Or some sort of special write barrier store op-code, idk.

mike_hearn•1y ago
It exists, that's called MPKs.
twoodfin•1y ago
I don’t think MPK’s will fit the need I have. Simply: Run some arbitrary, untrusted, non-sandboxed code in the same thread with assurance it can’t read page X. When that code completes and I’m back in code I trust, X is readable again.

Is that something MPK makes possible? The doc I’ve read suggests either your process can flip permission bits or it can’t. Great for avoiding out-of-sandbox reads. But if there’s arbitrary execution happening, why can’t that code flip the access to secrets back on?

mike_hearn•1y ago
Oracle Labs has tech that does that:

https://youtu.be/T05FI93MBI8?si=EieFgujaGiW2gbO8&t=958

The trick is to do a cascading disassembly of all untrusted code you'll execute to prove it can't change the MPK register.

twoodfin•1y ago
Wow. Neat trick and exactly the kind of thing I was looking for.

Thanks!

EDIT: Looks like this is the relevant paper from the Graal team: https://www.graalvm.org/resources/articles/binsweep.pdf

jdougan•1y ago
Is that something like the memory protection scheme on the Newton OS?
nyanpasu64•1y ago
Isn't not swapping page tables during a call precisely what the KPTI mitigations had to turn off for Meltdown mitigations?