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AMD acquires Taalas to boost inference performance by etching models in silicon

https://www.theregister.com/systems/2026/08/06/amd-acquires-ai-chip-startup-taalas-to-boost-infer...
546•itvision•10h ago•421 comments

Mario Meets Pareto

https://www.mayerowitz.io/blog/mario-meets-pareto
984•theanonymousone•19h ago•154 comments

Scientists discover Kelvin-Helmholtz Instability on the surface of the Sun

https://nso.edu/press-release/nsf-inouye-solar-telescope-enables-major-discovery-of-a-hidden-sola...
199•neversaydie•1d ago•41 comments

Taste Is All That's Left

https://notashelf.dev/posts/taste-is-all-thats-left
334•tsak•13h ago•252 comments

Atomic Clocks

https://www.nist.gov/atomic-clocks/how-do-atomic-clocks-work
22•teleforce•6d ago•7 comments

Bioengineered chewing gum may offer a way to fight HPV and other microbes

https://www.sciencedaily.com/releases/2026/08/260803080917.htm
97•Audiophilip•9h ago•18 comments

Software development with AI is starting to feel like cooking steak

https://blog.sydorets.com/en/posts/almost-no-skill-required-to-cook-a-steak/
331•yusyd•15h ago•364 comments

Reverse Jevons Paradox

https://mht.wtf/post/jevons/
6•martinhath•3d ago•1 comments

GitHub Actions and Pages are experiencing degraded availability

https://www.githubstatus.com/incidents/qcvjkzcs7j74
374•Footkerchief•14h ago•302 comments

Improving GPT‑5.6 Sol in ChatGPT, expanding GPT‑5.6 Luna access for free users

https://openai.com/index/improving-gpt-5-6-sol-in-chatgpt/
208•tedsanders•13h ago•151 comments

Welcoming the Nepalese Government to Have I Been Pwned

https://www.troyhunt.com/welcoming-the-nepalese-government-to-have-i-been-pwned/
133•gnabgib•8h ago•19 comments

I stopped trusting USB-C cable labels and started testing them

https://www.makeuseof.com/i-stopped-trusting-usb-c-cable-labels-started-testing-with-meter-instead/
139•baranul•3d ago•113 comments

Launch HN: ProvenMetal (YC S26) delivers circuit boards in days instead of weeks

https://provenmetal.com
196•willcarkner•14h ago•141 comments

Framework discloses data breach via Metabase 0-day

https://community.frame.work/t/framework-data-breach-discussion/83939
30•RobinHirst11•1h ago•3 comments

Why Estonians invite strangers into their back gardens each summer

https://www.bbc.com/travel/article/20260731-why-estonians-invite-strangers-into-their-backyards-e...
46•koolhead17•3d ago•14 comments

Herdr is joining Y Combinator. The runtime stays open

https://herdr.dev/blog/herdr-is-joining-y-combinator/
185•collinmanderson•11h ago•123 comments

Meta Ordered to Pay $942M to Address Harm to Kids from Social Media

https://www.wsj.com/tech/meta-ordered-to-pay-942-million-to-address-harm-to-kids-from-social-medi...
158•boplicity•6h ago•102 comments

Retired man plants trees on forgotten land, now it's Sao Paulo's largest park

https://timesofindia.indiatimes.com/world/rest-of-world/in-2003-a-retired-man-planted-trees-on-fo...
80•rmason•5d ago•26 comments

Humans missed 1 in 3 threats approving AI agent commands across 40k game runs

https://scalex.dev/blog/ai-agent-permissions-stats/
283•Wirbelwind•18h ago•200 comments

My phone detects going on a run as “someone snatching my phone and running off”

https://mastodon.gamedev.place/@rygorous/117047697255584965
116•luu•12h ago•210 comments

STV: A full-motion video codec for the Atari ST

https://medium.com/@jonas.eschenburg/stv-a-video-codec-for-the-atari-st-6e46355c50e4
37•indyjo•1w ago•4 comments

Learn how chips are made with this Rollercoaster Tycoon-inspired animation

https://laurentiugabriel.github.io/ChipTycoon/
133•laurentiurad•6d ago•26 comments

Quake – 30th Anniversary Update

https://slayersclub.bethesda.net/en-US/news/quake-30th-anniversary-update
266•dsubburam•10h ago•136 comments

Show HN: The Channels SDK – Bring Any Agent to Any Channel (Slack, MS Teams)

https://github.com/CopilotKit/channels-sdk
98•davidmckayv•14h ago•21 comments

Inside vLLM: Anatomy of a High-Throughput LLM Inference System (2025)

https://www.aleksagordic.com/blog/vllm
86•sebg•9h ago•5 comments

The simple elegance of the integrated timing belt loopback fastener

https://danielmangum.com/posts/integrated-timing-belt-loopback-fastener/
113•hasheddan•4d ago•23 comments

Pareto Front

https://en.wikipedia.org/wiki/Pareto_front
236•binyu•1w ago•96 comments

The Sylvester–Gallai Theorem

https://www.futilitycloset.com/2026/07/26/the-sylvester-gallai-theorem/
29•surprisetalk•6d ago•26 comments

Learning to fly FPV drones with AI flight coach

https://blog.divyendusingh.com/p/learning-to-fly-fpv-drones-with-ai
9•divyenduz•3d ago•7 comments

I've succesfully compiled Netscape 3.0.2 on a 64 Debian

https://www.reddit.com/r/netscape/comments/1ve7wkm/ive_succesfully_compiled_netscape_302_on_a_64/
8•zekrioca•55m ago•3 comments
Open in hackernews

How ZGC allocates memory for the Java heap

https://joelsiks.com/posts/zgc-heap-memory-allocation/
86•lichtenberger•1y ago

Comments

gopalv•1y ago
The 32x virtual memory to physical memory ratio plays into relocation and colored pointers (i.e pointers where some bits serve as flag bits).

Putting the actual data layouts in 44 bits out of 64 is a neat trick which relies on the allocator being aware of the mappings between physical and virtual addresses.

twoodfin•1y ago
When your comment and the article refer to “physical” addresses, those are physical in the context of the JVM, right? To the OS they’re virtual addresses in the JVM process space?
acchow•1y ago
Correct. ZGC has no way to escape from the virtualization by the kernel (assuming your hardware and kernel uses an MMU)
MBCook•1y ago
Thank you for the answer, I was wondering that as well.
hinkley•1y ago
In the beginning of the 32 bit revolution, when the future was here but unevenly distributed, there was a lot of talk about how 32 bit pointers would fundamentally change how people wrote code. Among other things it got rid of a bunch of odd bookkeeping, and if you don’t have to do the bookkeeping you don’t have to write the code in a way that supports it, so you can do other things.

Not too long after someone asked what sort of interesting changes 64 bit will bring. And I’ve been keeping that question in the back of my mind ever since.

Aliasing memory multiple times in order to do read or write barriers and make GC much cheaper is a pretty good one. But another one I know of is that one of the secrets of the L4 microkernel is that its IPC speed comes substantially from reducing the amount of TLB work that needs to be done to switch to another process running in a different address space. They use the same address space and only swap out the access rights which cuts the call overhead in half. It’s pretty easy to put a bunch of processes into a 64 bit address space and just throw each one a randomly located 4GB slice of RAM.

twoodfin•1y ago
Yeah, would love to see the CPU vendors invent some primitives to let user code pull those kinds of privilege isolation tricks within a single process and address space.

Something like: “From now on, code on these pages can only access data on these pages, and only return to/call into other code through these gates…”

hinkley•1y ago
Thread based seems like it at least should be possible.
ahartmetz•1y ago
I've had some ideas about avoiding format validation in IPC receivers if the data is encoded by trusted code, which is also the only code that has rights to send the IPC data / to connect to the receiver. I can't really think of an important problem that it would solve, though. DBus always validates received data, but it's not really meant or very suitable for large amounts of data anyway.
pron•1y ago
For relevant upcoming changes see Automatic Heap Sizing for ZGC: https://openjdk.org/jeps/8329758
twoodfin•1y ago
What I’m looking for is a way for a process to de/re-escalate its privileges to access memory, without an expensive context switch being required at the transition. The CPU would simply enforce different rules based on (say) the high-order bits of the instruction pointer.

Imagine a server process that wants to run some elaborate third-party content parser. It’d be great to be sure that no matter how buggy or malicious that code, it can’t leak the TLS keys.

Today, high-security architectures must use process isolation to achieve this kind of architectural guarantee, but even finely tuned IPC like L4’s is an order of magnitude slower than a predictable jump.

gpderetta•1y ago
For a brief moment Intel supported MPX which did something similar.

You can also play tricks with the virtualization hardware, bit it need kernel support.

Eventually we will get segments back again.

MarkSweep•1y ago
That would be pretty cool. Something like the Win32 function GetWriteWatch, but implemented in hardware instead of the page fault handler (I assume).

https://learn.microsoft.com/en-us/windows/win32/api/memoryap...

Or some sort of special write barrier store op-code, idk.

mike_hearn•1y ago
It exists, that's called MPKs.
twoodfin•1y ago
I don’t think MPK’s will fit the need I have. Simply: Run some arbitrary, untrusted, non-sandboxed code in the same thread with assurance it can’t read page X. When that code completes and I’m back in code I trust, X is readable again.

Is that something MPK makes possible? The doc I’ve read suggests either your process can flip permission bits or it can’t. Great for avoiding out-of-sandbox reads. But if there’s arbitrary execution happening, why can’t that code flip the access to secrets back on?

mike_hearn•1y ago
Oracle Labs has tech that does that:

https://youtu.be/T05FI93MBI8?si=EieFgujaGiW2gbO8&t=958

The trick is to do a cascading disassembly of all untrusted code you'll execute to prove it can't change the MPK register.

twoodfin•1y ago
Wow. Neat trick and exactly the kind of thing I was looking for.

Thanks!

EDIT: Looks like this is the relevant paper from the Graal team: https://www.graalvm.org/resources/articles/binsweep.pdf

jdougan•1y ago
Is that something like the memory protection scheme on the Newton OS?
nyanpasu64•1y ago
Isn't not swapping page tables during a call precisely what the KPTI mitigations had to turn off for Meltdown mitigations?