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Hardware backdoors in some x86 CPUs

https://github.com/xoreaxeaxeax/rosenbridge
69•epestr•1h ago•13 comments

A Physicist Rigged His Pet Hamster’s Wheel to Upload to Strava

https://www.runnersworld.com/news/a73355106/hamster-wheel-strava-running/
167•aanet•2d ago•30 comments

DeepSeek V4 Flash 0731

https://arcprize.org/results/deepseek-v4-flash-0731
609•tosh•15h ago•367 comments

U.S. Department of Energy Launches the Genesis Open Models Initiative

https://genesisopenmodels.anl.gov/
224•moelf•10h ago•77 comments

What happens if an entire class of workers loses faith in their careers

https://www.noemamag.com/why-is-everyone-in-tech-so-sad/
626•RickJWagner•20h ago•696 comments

Assembly Hall of Shame

https://github.com/xoreaxeaxeax/asm-hall-of-shame
336•piotrgrabowski•14h ago•83 comments

NASA figured out how to keep its Voyager 2 probe running for another year

https://www.space.com/space-exploration/voyager/nasa-figured-out-how-to-keep-its-48-year-old-voya...
222•wglb•7h ago•39 comments

Ancient Library – 1,060 Greek/Latin texts, click any word to parse it

https://ancientlibrary.net/
203•aagha•14h ago•63 comments

SupererDuperer

https://www.shirtpocket.com/blog/supererduperer
97•zdw•6d ago•19 comments

The Nixpkgs core team has disbanded

https://discourse.nixos.org/t/the-nixpkgs-core-team-has-disbanded/79413
285•Meleagris•7h ago•134 comments

Managing AI Coding Costs at Scale

https://www.databricks.com/blog/managing-ai-coding-costs-scale
233•moonikakiss•14h ago•201 comments

ao486: x86-compatible Verilog core implementing all features of a 486 SX (2014)

https://github.com/alfikpl/ao486
7•csmantle•6d ago•0 comments

From One Seed to a Thousand Leaves – Merkle's Authentication Tree

https://0xkrt26.github.io/math_behind_security/2026/08/03/merkle-tree.html
14•denismenace•3d ago•0 comments

Workers Drilling in Romania Broke into a Cave Sealed for 5.5M Years

https://travelandtannins.com/workers-drilling-in-romania-broke-into-a-cave-sealed-for-5-5-million...
70•yk•3d ago•29 comments

2027 memory capacity is reportedly sold out

https://www.ign.com/articles/ramageddon-continues-another-year-as-2027-memory-capacity-is-reporte...
351•inigyou•1d ago•312 comments

An all-sky map of half a million supermassive black holes

https://www.sdss.org/black-hole-mapper-release-20/
166•MarcoDewey•17h ago•37 comments

Responding to the next frontier of critical cyber capabilities

https://openai.com/index/responding-next-frontier-critical-cyber-capabilities/
182•artninja1988•16h ago•175 comments

Carl's Required Reading

https://carlkolon.com/reading/
162•cckolon•6d ago•20 comments

Oracle bans AI-generated code from OpenJDK

https://app.dealroom.co/news/feed/oracle-bans-ai-generated-code-from-openjdk-despite-ellison-s-cl...
465•delduca•15h ago•322 comments

Radical Study Suggests Life on Earth Arose Twice

https://www.sciencealert.com/radical-study-suggests-life-on-earth-arose-from-non-living-matter-twice
139•jnord•20h ago•99 comments

Making Postgres 300x faster for analytics: batching, operator fusion, and SIMD

https://malisper.me/how-we-made-postgres-hundreds-of-times-faster-the-query-engine/
285•poly2it•21h ago•136 comments

Psychological Warfare in Reverse Engineering (2015)

https://github.com/xoreaxeaxeax/repsych
69•theanonymousone•14h ago•4 comments

Kitesurf: Agent-first browser that runs in V8 isolates

https://blog.cloudflare.com/kitesurf/
191•m3h•22h ago•50 comments

Water system controllers don't belong on the internet, says ex-NSA chief

https://www.theregister.com/security/2026/08/07/water-system-controllers-dont-belong-on-the-inter...
188•Bender•11h ago•125 comments

Guarded Methods in OCaml (2025)

https://xvw.lol/en/articles/oop-refl.html
68•birdculture•4d ago•6 comments

Games at the press of a button: The Rip-O-Bot (1989)

https://blog.gingerbeardman.com/2026/08/02/games-at-the-press-of-a-button-the-rip-o-bot/
32•msephton•5d ago•9 comments

New Mexico court orders Meta to pay $567m over harms to children’s mental health

https://www.theguardian.com/technology/2026/aug/06/new-mexico-court-meta
758•boplicity•1d ago•405 comments

Möbius-Strip Crosswords

https://quuxplusone.github.io/blog/2026/08/04/mobius-crossword/
72•ibobev•17h ago•10 comments

Mythos social engineering AISI INC-2026-07-28-01

https://web.archive.org/web/20260731053721/http://github.com/ancaferro/myNetwork/pull/3
60•dnnehgf•5h ago•17 comments

Show HN: Wyzer Programming Language

https://github.com/Wyzer-Lang/wyzer
197•v0id_isgood•20h ago•108 comments
Open in hackernews

How ZGC allocates memory for the Java heap

https://joelsiks.com/posts/zgc-heap-memory-allocation/
86•lichtenberger•1y ago

Comments

gopalv•1y ago
The 32x virtual memory to physical memory ratio plays into relocation and colored pointers (i.e pointers where some bits serve as flag bits).

Putting the actual data layouts in 44 bits out of 64 is a neat trick which relies on the allocator being aware of the mappings between physical and virtual addresses.

twoodfin•1y ago
When your comment and the article refer to “physical” addresses, those are physical in the context of the JVM, right? To the OS they’re virtual addresses in the JVM process space?
acchow•1y ago
Correct. ZGC has no way to escape from the virtualization by the kernel (assuming your hardware and kernel uses an MMU)
MBCook•1y ago
Thank you for the answer, I was wondering that as well.
hinkley•1y ago
In the beginning of the 32 bit revolution, when the future was here but unevenly distributed, there was a lot of talk about how 32 bit pointers would fundamentally change how people wrote code. Among other things it got rid of a bunch of odd bookkeeping, and if you don’t have to do the bookkeeping you don’t have to write the code in a way that supports it, so you can do other things.

Not too long after someone asked what sort of interesting changes 64 bit will bring. And I’ve been keeping that question in the back of my mind ever since.

Aliasing memory multiple times in order to do read or write barriers and make GC much cheaper is a pretty good one. But another one I know of is that one of the secrets of the L4 microkernel is that its IPC speed comes substantially from reducing the amount of TLB work that needs to be done to switch to another process running in a different address space. They use the same address space and only swap out the access rights which cuts the call overhead in half. It’s pretty easy to put a bunch of processes into a 64 bit address space and just throw each one a randomly located 4GB slice of RAM.

twoodfin•1y ago
Yeah, would love to see the CPU vendors invent some primitives to let user code pull those kinds of privilege isolation tricks within a single process and address space.

Something like: “From now on, code on these pages can only access data on these pages, and only return to/call into other code through these gates…”

hinkley•1y ago
Thread based seems like it at least should be possible.
ahartmetz•1y ago
I've had some ideas about avoiding format validation in IPC receivers if the data is encoded by trusted code, which is also the only code that has rights to send the IPC data / to connect to the receiver. I can't really think of an important problem that it would solve, though. DBus always validates received data, but it's not really meant or very suitable for large amounts of data anyway.
pron•1y ago
For relevant upcoming changes see Automatic Heap Sizing for ZGC: https://openjdk.org/jeps/8329758
twoodfin•1y ago
What I’m looking for is a way for a process to de/re-escalate its privileges to access memory, without an expensive context switch being required at the transition. The CPU would simply enforce different rules based on (say) the high-order bits of the instruction pointer.

Imagine a server process that wants to run some elaborate third-party content parser. It’d be great to be sure that no matter how buggy or malicious that code, it can’t leak the TLS keys.

Today, high-security architectures must use process isolation to achieve this kind of architectural guarantee, but even finely tuned IPC like L4’s is an order of magnitude slower than a predictable jump.

gpderetta•1y ago
For a brief moment Intel supported MPX which did something similar.

You can also play tricks with the virtualization hardware, bit it need kernel support.

Eventually we will get segments back again.

MarkSweep•1y ago
That would be pretty cool. Something like the Win32 function GetWriteWatch, but implemented in hardware instead of the page fault handler (I assume).

https://learn.microsoft.com/en-us/windows/win32/api/memoryap...

Or some sort of special write barrier store op-code, idk.

mike_hearn•1y ago
It exists, that's called MPKs.
twoodfin•1y ago
I don’t think MPK’s will fit the need I have. Simply: Run some arbitrary, untrusted, non-sandboxed code in the same thread with assurance it can’t read page X. When that code completes and I’m back in code I trust, X is readable again.

Is that something MPK makes possible? The doc I’ve read suggests either your process can flip permission bits or it can’t. Great for avoiding out-of-sandbox reads. But if there’s arbitrary execution happening, why can’t that code flip the access to secrets back on?

mike_hearn•1y ago
Oracle Labs has tech that does that:

https://youtu.be/T05FI93MBI8?si=EieFgujaGiW2gbO8&t=958

The trick is to do a cascading disassembly of all untrusted code you'll execute to prove it can't change the MPK register.

twoodfin•1y ago
Wow. Neat trick and exactly the kind of thing I was looking for.

Thanks!

EDIT: Looks like this is the relevant paper from the Graal team: https://www.graalvm.org/resources/articles/binsweep.pdf

jdougan•1y ago
Is that something like the memory protection scheme on the Newton OS?
nyanpasu64•1y ago
Isn't not swapping page tables during a call precisely what the KPTI mitigations had to turn off for Meltdown mitigations?