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Cloud in a Bottle: making self-hosting accessible to everyone

https://cloudinabottle.org/blog/launch-post
86•zplizzi•1h ago•33 comments

The revolt of the reader

https://bcantrill.dtrace.org/2026/09/05/the-revolt-of-the-reader/
99•chmaynard•4h ago•27 comments

Private German rocket makes history, reaches orbit from European soil

https://www.space.com/space-exploration/launches-spacecraft/isar-aerospace-second-launch-norway-a...
366•bookmtn•5h ago•187 comments

Learn Programming with OCaml

https://usr.lmf.cnrs.fr/lpo/
175•elvis70•8h ago•73 comments

The "$60 Gaming PC" – AMD BC-250 (2025)

https://devquasar.com/hardware/the-60-gaming-pc-amd-bc-250/
280•networked•12h ago•85 comments

Finite time blowup for an averaged three-dimensional Navier-Stokes equation (2014)

https://terrytao.wordpress.com/2014/02/04/finite-time-blowup-for-an-averaged-three-dimensional-na...
57•gmays•5h ago•21 comments

How Swiss tables work in Go built-in map

https://victoriametrics.com/blog/go-swiss-table-map/index.html
43•valyala•2d ago•3 comments

Discovery of a new OpenAI agent message board

https://collusion.wiki/
2111•moultano•1d ago•1515 comments

Visualizing Rust's Vtables: How dyn Trait Works In Memory

https://sofiabelen.github.io/projects/visualizing-rusts-vtables-how-dyn-trait-works-in-memory/
133•torutofu•12h ago•19 comments

Balrogg: Demonically compacting (up to 15%) lossless Vorbis/Opus recompressor

https://github.com/iczelia/balrogg
63•palaiologos•2d ago•8 comments

Actively exploited sandbox RCE in all Chromium versions

https://nvd.nist.gov/vuln/detail/cve-2026-85046
743•negura•1d ago•441 comments

Nitter has more working instances than before the takedowns

https://codeberg.org/mv12star/shitter/wiki/Instances
628•Cider9986•1d ago•306 comments

Show HN: Fly By – retro biplane flying game

https://michaelteter.com/flyby.html
45•michaelteter•4d ago•30 comments

The Double Matthew Walker Knot by Fable 5.1

https://claude.ai/public/artifacts/06fd26a5-403c-47c8-af49-dcf6c35ec55c
18•nemesis17•2d ago•9 comments

OKF Agent Memory – Git-native persistent memory for AI coding agents

https://github.com/okf-memory/okf-agent-memory
31•okf_memory•3h ago•13 comments

LLMs as a Cognitive Virus

https://arxiv.org/abs/2609.03344
174•canjobear•5h ago•152 comments

Delidded Intel I9-14900KS CT Scan

https://www.lttlabs.com/articles/2026/09/02/delidded-intel-i9-14900ks
63•willx86•3d ago•1 comments

Terpstra Keyboard

http://terpstrakeyboard.com/
114•cl3misch•15h ago•54 comments

CHC5: Open Camera System – Image Sensor Specification Comparison

https://www.circuitvalley.com/2026/08/chc5-open-camera-sensor-comparison-specification.html
10•devoxel•3d ago•1 comments

Isar Aerospace launch into orbit [video]

https://www.youtube.com/watch?v=Ss1DUqLjecc
86•stefan_•5h ago•18 comments

Stopping the Unstoppable: When an unstoppable force meets a dashpot snubber

https://practical.engineering/blog/2026/9/1/stopping-the-unstoppable
51•crescit_eundo•4d ago•6 comments

ISAR Aerospace 5 Sept Mission Onward and Upward

https://isaraerospace.com/mission-updates-overview
16•t43562•6h ago•1 comments

Topologist's Map of the World

https://www.futilitycloset.com/2026/09/01/small-world-20/
23•beardyw•4d ago•10 comments

Chrome again exempts Google from user site data settings

https://lapcatsoftware.com/articles/2026/9/1.html
21•ExMachina73•2h ago•0 comments

Statichost.eu – European static site hosting

https://www.statichost.eu/
444•p4bl0•1d ago•201 comments

Steffen's Polyhedron

https://www.gregegan.net/SCIENCE/Steffen/Steffen.html
51•pavel_lishin•2d ago•5 comments

Can AI design circuit boards yet?

https://eebench.org/blog/can-ai-design-circuit-boards-yet/
380•iopapa•1d ago•208 comments

A bizarre Commodore 64 peripheral, a mime, and some pretty bad ads

https://buttondown.com/suchbadtechads/archive/spartan-and-the-mime/
78•rfarley04•13h ago•10 comments

Singapore subway (mrt) information display types

https://www.sgtrains.com/technology-infosys.html
44•gregorvand•3d ago•16 comments

.gitignore Everything by Default

https://packagemain.tech/p/gitignore-everything-by-default
156•der_gopher•12h ago•155 comments
Open in hackernews

How ZGC allocates memory for the Java heap

https://joelsiks.com/posts/zgc-heap-memory-allocation/
86•lichtenberger•1y ago

Comments

gopalv•1y ago
The 32x virtual memory to physical memory ratio plays into relocation and colored pointers (i.e pointers where some bits serve as flag bits).

Putting the actual data layouts in 44 bits out of 64 is a neat trick which relies on the allocator being aware of the mappings between physical and virtual addresses.

twoodfin•1y ago
When your comment and the article refer to “physical” addresses, those are physical in the context of the JVM, right? To the OS they’re virtual addresses in the JVM process space?
acchow•1y ago
Correct. ZGC has no way to escape from the virtualization by the kernel (assuming your hardware and kernel uses an MMU)
MBCook•1y ago
Thank you for the answer, I was wondering that as well.
hinkley•1y ago
In the beginning of the 32 bit revolution, when the future was here but unevenly distributed, there was a lot of talk about how 32 bit pointers would fundamentally change how people wrote code. Among other things it got rid of a bunch of odd bookkeeping, and if you don’t have to do the bookkeeping you don’t have to write the code in a way that supports it, so you can do other things.

Not too long after someone asked what sort of interesting changes 64 bit will bring. And I’ve been keeping that question in the back of my mind ever since.

Aliasing memory multiple times in order to do read or write barriers and make GC much cheaper is a pretty good one. But another one I know of is that one of the secrets of the L4 microkernel is that its IPC speed comes substantially from reducing the amount of TLB work that needs to be done to switch to another process running in a different address space. They use the same address space and only swap out the access rights which cuts the call overhead in half. It’s pretty easy to put a bunch of processes into a 64 bit address space and just throw each one a randomly located 4GB slice of RAM.

twoodfin•1y ago
Yeah, would love to see the CPU vendors invent some primitives to let user code pull those kinds of privilege isolation tricks within a single process and address space.

Something like: “From now on, code on these pages can only access data on these pages, and only return to/call into other code through these gates…”

hinkley•1y ago
Thread based seems like it at least should be possible.
ahartmetz•1y ago
I've had some ideas about avoiding format validation in IPC receivers if the data is encoded by trusted code, which is also the only code that has rights to send the IPC data / to connect to the receiver. I can't really think of an important problem that it would solve, though. DBus always validates received data, but it's not really meant or very suitable for large amounts of data anyway.
pron•1y ago
For relevant upcoming changes see Automatic Heap Sizing for ZGC: https://openjdk.org/jeps/8329758
twoodfin•1y ago
What I’m looking for is a way for a process to de/re-escalate its privileges to access memory, without an expensive context switch being required at the transition. The CPU would simply enforce different rules based on (say) the high-order bits of the instruction pointer.

Imagine a server process that wants to run some elaborate third-party content parser. It’d be great to be sure that no matter how buggy or malicious that code, it can’t leak the TLS keys.

Today, high-security architectures must use process isolation to achieve this kind of architectural guarantee, but even finely tuned IPC like L4’s is an order of magnitude slower than a predictable jump.

gpderetta•1y ago
For a brief moment Intel supported MPX which did something similar.

You can also play tricks with the virtualization hardware, bit it need kernel support.

Eventually we will get segments back again.

MarkSweep•1y ago
That would be pretty cool. Something like the Win32 function GetWriteWatch, but implemented in hardware instead of the page fault handler (I assume).

https://learn.microsoft.com/en-us/windows/win32/api/memoryap...

Or some sort of special write barrier store op-code, idk.

mike_hearn•1y ago
It exists, that's called MPKs.
twoodfin•1y ago
I don’t think MPK’s will fit the need I have. Simply: Run some arbitrary, untrusted, non-sandboxed code in the same thread with assurance it can’t read page X. When that code completes and I’m back in code I trust, X is readable again.

Is that something MPK makes possible? The doc I’ve read suggests either your process can flip permission bits or it can’t. Great for avoiding out-of-sandbox reads. But if there’s arbitrary execution happening, why can’t that code flip the access to secrets back on?

mike_hearn•1y ago
Oracle Labs has tech that does that:

https://youtu.be/T05FI93MBI8?si=EieFgujaGiW2gbO8&t=958

The trick is to do a cascading disassembly of all untrusted code you'll execute to prove it can't change the MPK register.

twoodfin•1y ago
Wow. Neat trick and exactly the kind of thing I was looking for.

Thanks!

EDIT: Looks like this is the relevant paper from the Graal team: https://www.graalvm.org/resources/articles/binsweep.pdf

jdougan•1y ago
Is that something like the memory protection scheme on the Newton OS?
nyanpasu64•1y ago
Isn't not swapping page tables during a call precisely what the KPTI mitigations had to turn off for Meltdown mitigations?