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I’m joining OpenAI

https://steipete.me/posts/2026/openclaw
823•mfiguiere•8h ago•560 comments

Magnus Carlsen Wins the Freestyle (Chess960) World Championship

https://www.fide.com/magnus-carlsen-wins-2026-fide-freestyle-world-championship/
216•prophylaxis•8h ago•129 comments

Arm wants a bigger slice of the chip business

https://www.economist.com/business/2026/02/12/arm-wants-a-bigger-slice-of-the-chip-business
48•andsoitis•3h ago•22 comments

Modern CSS Code Snippets: Stop writing CSS like it's 2015

https://modern-css.com
334•eustoria•12h ago•133 comments

LT6502: A 6502-based homebrew laptop

https://github.com/TechPaula/LT6502
336•classichasclass•13h ago•149 comments

Audio is the one area small labs are winning

https://www.amplifypartners.com/blog-posts/arming-the-rebels-with-gpus-gradium-kyutai-and-audio-ai
158•rocauc•3d ago•29 comments

How long do job postings stay open?

https://corvi.careers/blog/job_open_days_by_category_feb_2026/
17•sp1982•1d ago•13 comments

I gave Claude access to my pen plotter

https://harmonique.one/posts/i-gave-claude-access-to-my-pen-plotter
148•futurecat•2d ago•76 comments

Error payloads in Zig

https://srcreigh.ca/posts/error-payloads-in-zig/
66•srcreigh•7h ago•24 comments

Databases should contain their own Metadata – Use SQL Everywhere

https://floedb.ai/blog/databases-should-contain-their-own-metadata-instrumentation-in-floe
11•matheusalmeida•4d ago•3 comments

I Love Board Games: A Personal Obsession Explained by Psychology

https://www.thesswnetwork.com/post/why-i-love-board-games-a-personal-obsession-explained-by-psych...
36•Propolice•4d ago•23 comments

Show HN: Microgpt is a GPT you can visualize in the browser

https://microgpt.boratto.ca
155•b44•11h ago•13 comments

Transforming a Clojure Database into a Library with GraalVM Native Image and FFI

https://avelino.run/chrondb-polyglot-ffi-clojure-graalvm-native-image/
35•PaulHoule•4d ago•2 comments

Why does aluminum foil have one shiny side and one with a matte finish?

https://bookofjoe2.blogspot.com/2025/10/why-does-aluminum-foil-have-one-shiny.html
7•surprisetalk•4d ago•11 comments

EU bans the destruction of unsold apparel, clothing, accessories and footwear

https://environment.ec.europa.eu/news/new-eu-rules-stop-destruction-unsold-clothes-and-shoes-2026...
859•giuliomagnifico•13h ago•598 comments

Radio host David Greene says Google's NotebookLM tool stole his voice

https://www.washingtonpost.com/technology/2026/02/15/david-greene-google-ai-podcast/
140•mikhael•12h ago•79 comments

Pocketblue – Fedora Atomic for mobile devices

https://github.com/pocketblue/pocketblue
84•nikodunk•13h ago•15 comments

Real-time PathTracing with global illumination in WebGL

https://erichlof.github.io/THREE.js-PathTracing-Renderer/
146•tobr•3d ago•13 comments

Gwtar: A static efficient single-file HTML format

https://gwern.net/gwtar
211•theblazehen•14h ago•70 comments

GNU Pies – Program Invocation and Execution Supervisor

https://www.gnu.org.ua/software/pies/
75•smartmic•9h ago•50 comments

Show HN: Knock-Knock.net – Visualizing the bots knocking on my server's door

https://knock-knock.net
124•djkurlander•13h ago•52 comments

Show HN: VOOG – Moog-style polyphonic synthesizer in Python with tkinter GUI

https://github.com/gpasquero/voog
76•gpasquero•10h ago•24 comments

Editor's Note: Retraction of article containing fabricated quotations

https://arstechnica.com/staff/2026/02/editors-note-retraction-of-article-containing-fabricated-qu...
210•bikenaga•11h ago•151 comments

Amazon's Ring and Google's Nest reveal the severity of U.S. surveillance state

https://greenwald.substack.com/p/amazons-ring-and-googles-nest-unwittingly
771•mikece•17h ago•564 comments

I fixed Windows native development

https://marler8997.github.io/blog/fixed-windows/
713•deevus•19h ago•340 comments

Language a Wood for Thought: Susan Howe's Work

https://www.poetryfoundation.org/articles/1769037/language-a-wood-for-thought
22•apollinaire•4d ago•1 comments

Benchmarking Automatic Typesetting Systems

https://news.speedata.de/2026/02/10/typesetting-benchmark/
12•patrickg•5d ago•4 comments

Towards Autonomous Mathematics Research

https://arxiv.org/abs/2602.10177
90•gmays•11h ago•48 comments

Hideki Sato, designer of all Sega's consoles, has died

https://www.videogameschronicle.com/news/hideki-sato-designer-of-segas-consoles-dies-age-75/
383•magoghm•14h ago•38 comments

Why I don't think AGI is imminent

https://dlants.me/agi-not-imminent.html
63•anonymid•6h ago•140 comments
Open in hackernews

How ZGC allocates memory for the Java heap

https://joelsiks.com/posts/zgc-heap-memory-allocation/
86•lichtenberger•9mo ago

Comments

gopalv•9mo ago
The 32x virtual memory to physical memory ratio plays into relocation and colored pointers (i.e pointers where some bits serve as flag bits).

Putting the actual data layouts in 44 bits out of 64 is a neat trick which relies on the allocator being aware of the mappings between physical and virtual addresses.

twoodfin•9mo ago
When your comment and the article refer to “physical” addresses, those are physical in the context of the JVM, right? To the OS they’re virtual addresses in the JVM process space?
acchow•9mo ago
Correct. ZGC has no way to escape from the virtualization by the kernel (assuming your hardware and kernel uses an MMU)
MBCook•9mo ago
Thank you for the answer, I was wondering that as well.
hinkley•9mo ago
In the beginning of the 32 bit revolution, when the future was here but unevenly distributed, there was a lot of talk about how 32 bit pointers would fundamentally change how people wrote code. Among other things it got rid of a bunch of odd bookkeeping, and if you don’t have to do the bookkeeping you don’t have to write the code in a way that supports it, so you can do other things.

Not too long after someone asked what sort of interesting changes 64 bit will bring. And I’ve been keeping that question in the back of my mind ever since.

Aliasing memory multiple times in order to do read or write barriers and make GC much cheaper is a pretty good one. But another one I know of is that one of the secrets of the L4 microkernel is that its IPC speed comes substantially from reducing the amount of TLB work that needs to be done to switch to another process running in a different address space. They use the same address space and only swap out the access rights which cuts the call overhead in half. It’s pretty easy to put a bunch of processes into a 64 bit address space and just throw each one a randomly located 4GB slice of RAM.

twoodfin•9mo ago
Yeah, would love to see the CPU vendors invent some primitives to let user code pull those kinds of privilege isolation tricks within a single process and address space.

Something like: “From now on, code on these pages can only access data on these pages, and only return to/call into other code through these gates…”

hinkley•9mo ago
Thread based seems like it at least should be possible.
ahartmetz•9mo ago
I've had some ideas about avoiding format validation in IPC receivers if the data is encoded by trusted code, which is also the only code that has rights to send the IPC data / to connect to the receiver. I can't really think of an important problem that it would solve, though. DBus always validates received data, but it's not really meant or very suitable for large amounts of data anyway.
twoodfin•9mo ago
What I’m looking for is a way for a process to de/re-escalate its privileges to access memory, without an expensive context switch being required at the transition. The CPU would simply enforce different rules based on (say) the high-order bits of the instruction pointer.

Imagine a server process that wants to run some elaborate third-party content parser. It’d be great to be sure that no matter how buggy or malicious that code, it can’t leak the TLS keys.

Today, high-security architectures must use process isolation to achieve this kind of architectural guarantee, but even finely tuned IPC like L4’s is an order of magnitude slower than a predictable jump.

gpderetta•9mo ago
For a brief moment Intel supported MPX which did something similar.

You can also play tricks with the virtualization hardware, bit it need kernel support.

Eventually we will get segments back again.

MarkSweep•9mo ago
That would be pretty cool. Something like the Win32 function GetWriteWatch, but implemented in hardware instead of the page fault handler (I assume).

https://learn.microsoft.com/en-us/windows/win32/api/memoryap...

Or some sort of special write barrier store op-code, idk.

mike_hearn•9mo ago
It exists, that's called MPKs.
twoodfin•9mo ago
I don’t think MPK’s will fit the need I have. Simply: Run some arbitrary, untrusted, non-sandboxed code in the same thread with assurance it can’t read page X. When that code completes and I’m back in code I trust, X is readable again.

Is that something MPK makes possible? The doc I’ve read suggests either your process can flip permission bits or it can’t. Great for avoiding out-of-sandbox reads. But if there’s arbitrary execution happening, why can’t that code flip the access to secrets back on?

mike_hearn•9mo ago
Oracle Labs has tech that does that:

https://youtu.be/T05FI93MBI8?si=EieFgujaGiW2gbO8&t=958

The trick is to do a cascading disassembly of all untrusted code you'll execute to prove it can't change the MPK register.

twoodfin•9mo ago
Wow. Neat trick and exactly the kind of thing I was looking for.

Thanks!

EDIT: Looks like this is the relevant paper from the Graal team: https://www.graalvm.org/resources/articles/binsweep.pdf

jdougan•9mo ago
Is that something like the memory protection scheme on the Newton OS?
nyanpasu64•9mo ago
Isn't not swapping page tables during a call precisely what the KPTI mitigations had to turn off for Meltdown mitigations?
pron•9mo ago
For relevant upcoming changes see Automatic Heap Sizing for ZGC: https://openjdk.org/jeps/8329758