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I've factored the RSA keys of a Certificate Authority from the 90s

https://mcpherrin.ca/2026/09/07/rsa.html
287•ahlCVA•7h ago•50 comments

Mistral raises €3B

https://mistral.ai/news/mistral-makes-sovereign-open-weight-ai-to-frontier/
370•kuberwastaken•3h ago•230 comments

My Feed, My Way

https://www.pm.gov.au/media/my-feed-my-way
102•dotcoma•3h ago•63 comments

We have a year to fix security everywhere

https://jyn.dev/a-year-to-fix-security/
197•saikatsg•3h ago•157 comments

UAE-based Falcon AI NSFW classifier among top global open-source models (2025)

https://www.middleeastainews.com/p/uae-ai-model-tops-50-million-monthly
15•instagraham•1h ago•7 comments

Multi-Agents LLM Financial Trading Framework

https://github.com/TauricResearch/TradingAgents
36•fittingopposite•3h ago•24 comments

TALA Is Open-Source

https://d2lang.com/blog/tala-is-open-source/
210•alixanderwang•8h ago•14 comments

There's a new "Google Jail" for independent wikis

https://weirdgloop.org/blog/google-jail
100•pizzaiolo•6h ago•38 comments

How well do agents use test/verification techniques?

https://danluu.com/agentic-testing/
72•vinhnx•5h ago•20 comments

We built our house for LAN parties

https://lanparty.house/
21•fittingopposite•2d ago•8 comments

Arm Mali G2-Ultra NX GPU: desktop-class mobile gameplay with AI-native graphics

https://newsroom.arm.com/blog/arm-mali-g2-ultra-nx-ai-native-mobile-graphics
35•Re-Tails•4h ago•20 comments

Watch Los Angeles get built, one building at a time (1880–2026)

https://lax-skyline.parcelscope.net/
286•rustywasm•13h ago•141 comments

Understanding Computer Memory Architecture and SSD Internals

https://codingpirate.com/understanding-computer-memory-architecture-ac9320110787
33•Deeptiman•1d ago•2 comments

Jellyfin 12.0

https://jellyfin.org/posts/jellyfin-release-12.0/
330•0xC0ncord•6h ago•133 comments

Leaving VMware just got harder after Broadcom pulled VDDK downloads

https://www.virtualizationhowto.com/2026/09/leaving-vmware-just-got-harder-after-broadcom-pulled-...
182•josephcsible•12h ago•75 comments

Navier-Stokes – Tristan Buckmaster [pdf]

https://cims.nyu.edu/~tristanb/statement.pdf
193•procedurecall•2h ago•89 comments

The VMs Powering Mobile Agents (Instinct, Claude Code)

https://rohanadwankar.github.io/posts/platforms.html
24•RohanAdwankar•3h ago•6 comments

WeatherNext 3

https://deepmind.google/science/weathernext/
319•matthieu_bl•4d ago•76 comments

216M Spy TVs – The LG Smart TV Problem [video]

https://www.youtube.com/watch?v=6IFVTcM28KA
738•treve•1d ago•898 comments

John Margolies' photographs of roadside America

https://publicdomainreview.org/collection/john-margolies-photographs-of-roadside-america/
78•duck•4d ago•19 comments

Scientists observe Einstein's gravity in the quantum world

https://www.ox.ac.uk/news/2026-08-28-scientists-observe-einsteins-gravity-in-the-quantum-world
210•mudil•3d ago•53 comments

Extinct Tasmanian tiger's 'snap' unlike any living mammal's bite

https://www.cnn.com/2026/09/02/science/tasmanian-tiger-skull-bite-force
26•cisc•4d ago•6 comments

GamersNexus and LG: Or why rooting your TV is a bad idea

https://leaflet.pub/p/did:plc:yhgc5rlqhoezrx6fbawajxlh/3muwrqenzfk2n
79•drasticactions•4h ago•68 comments

Trusting-Trust Attack against an Entire Linux Distribution

https://arxiv.org/abs/2607.24888
204•signa11•2d ago•41 comments

Feather Atlas

https://www.fws.gov/lab/featheratlas/identify.html
8•bookofjoe•1d ago•1 comments

I tested 10 model/harness combinations on the same Three.js task

https://alvins82.github.io/hangar-harness-model-tests/
70•alvins82•4h ago•44 comments

My business partner sent a 5K vibe-coded PR that he didn't even test

https://ycj.bearblog.dev/ai-again/
34•yhcj•6h ago•33 comments

Emacs Bedrock 2.0

https://lambdaland.org/posts/2026-09-06-bedrock-v2/
106•ashton314•12h ago•13 comments

Colorlight 5A-75B: A dive into a popular low-cost ECP5 (FPGA) development board

https://blog.yosyshq.com/p/colorlight-part-1/
35•gregsadetsky•3d ago•7 comments

Icy Moons Are Ocean Worlds

https://mceglowski.substack.com/p/icy-moons-are-ocean-worlds
172•worldvoyageur•1d ago•20 comments
Open in hackernews

How ZGC allocates memory for the Java heap

https://joelsiks.com/posts/zgc-heap-memory-allocation/
86•lichtenberger•1y ago

Comments

gopalv•1y ago
The 32x virtual memory to physical memory ratio plays into relocation and colored pointers (i.e pointers where some bits serve as flag bits).

Putting the actual data layouts in 44 bits out of 64 is a neat trick which relies on the allocator being aware of the mappings between physical and virtual addresses.

twoodfin•1y ago
When your comment and the article refer to “physical” addresses, those are physical in the context of the JVM, right? To the OS they’re virtual addresses in the JVM process space?
acchow•1y ago
Correct. ZGC has no way to escape from the virtualization by the kernel (assuming your hardware and kernel uses an MMU)
MBCook•1y ago
Thank you for the answer, I was wondering that as well.
hinkley•1y ago
In the beginning of the 32 bit revolution, when the future was here but unevenly distributed, there was a lot of talk about how 32 bit pointers would fundamentally change how people wrote code. Among other things it got rid of a bunch of odd bookkeeping, and if you don’t have to do the bookkeeping you don’t have to write the code in a way that supports it, so you can do other things.

Not too long after someone asked what sort of interesting changes 64 bit will bring. And I’ve been keeping that question in the back of my mind ever since.

Aliasing memory multiple times in order to do read or write barriers and make GC much cheaper is a pretty good one. But another one I know of is that one of the secrets of the L4 microkernel is that its IPC speed comes substantially from reducing the amount of TLB work that needs to be done to switch to another process running in a different address space. They use the same address space and only swap out the access rights which cuts the call overhead in half. It’s pretty easy to put a bunch of processes into a 64 bit address space and just throw each one a randomly located 4GB slice of RAM.

twoodfin•1y ago
Yeah, would love to see the CPU vendors invent some primitives to let user code pull those kinds of privilege isolation tricks within a single process and address space.

Something like: “From now on, code on these pages can only access data on these pages, and only return to/call into other code through these gates…”

hinkley•1y ago
Thread based seems like it at least should be possible.
ahartmetz•1y ago
I've had some ideas about avoiding format validation in IPC receivers if the data is encoded by trusted code, which is also the only code that has rights to send the IPC data / to connect to the receiver. I can't really think of an important problem that it would solve, though. DBus always validates received data, but it's not really meant or very suitable for large amounts of data anyway.
pron•1y ago
For relevant upcoming changes see Automatic Heap Sizing for ZGC: https://openjdk.org/jeps/8329758
twoodfin•1y ago
What I’m looking for is a way for a process to de/re-escalate its privileges to access memory, without an expensive context switch being required at the transition. The CPU would simply enforce different rules based on (say) the high-order bits of the instruction pointer.

Imagine a server process that wants to run some elaborate third-party content parser. It’d be great to be sure that no matter how buggy or malicious that code, it can’t leak the TLS keys.

Today, high-security architectures must use process isolation to achieve this kind of architectural guarantee, but even finely tuned IPC like L4’s is an order of magnitude slower than a predictable jump.

gpderetta•1y ago
For a brief moment Intel supported MPX which did something similar.

You can also play tricks with the virtualization hardware, bit it need kernel support.

Eventually we will get segments back again.

MarkSweep•1y ago
That would be pretty cool. Something like the Win32 function GetWriteWatch, but implemented in hardware instead of the page fault handler (I assume).

https://learn.microsoft.com/en-us/windows/win32/api/memoryap...

Or some sort of special write barrier store op-code, idk.

mike_hearn•1y ago
It exists, that's called MPKs.
twoodfin•1y ago
I don’t think MPK’s will fit the need I have. Simply: Run some arbitrary, untrusted, non-sandboxed code in the same thread with assurance it can’t read page X. When that code completes and I’m back in code I trust, X is readable again.

Is that something MPK makes possible? The doc I’ve read suggests either your process can flip permission bits or it can’t. Great for avoiding out-of-sandbox reads. But if there’s arbitrary execution happening, why can’t that code flip the access to secrets back on?

mike_hearn•1y ago
Oracle Labs has tech that does that:

https://youtu.be/T05FI93MBI8?si=EieFgujaGiW2gbO8&t=958

The trick is to do a cascading disassembly of all untrusted code you'll execute to prove it can't change the MPK register.

twoodfin•1y ago
Wow. Neat trick and exactly the kind of thing I was looking for.

Thanks!

EDIT: Looks like this is the relevant paper from the Graal team: https://www.graalvm.org/resources/articles/binsweep.pdf

jdougan•1y ago
Is that something like the memory protection scheme on the Newton OS?
nyanpasu64•1y ago
Isn't not swapping page tables during a call precisely what the KPTI mitigations had to turn off for Meltdown mitigations?