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Running Claude Code dangerously (safely)

https://blog.emilburzo.com/2026/01/running-claude-code-dangerously-safely/
48•emilburzo•1h ago•39 comments

I'm addicted to being useful

https://www.seangoedecke.com/addicted-to-being-useful/
71•swah•2h ago•39 comments

Linux kernel framework for PCIe device emulation, in userspace

https://github.com/cakehonolulu/pciem
105•71bw•5h ago•30 comments

Level S4 solar radiation event

https://www.swpc.noaa.gov/news/g4-severe-geomagnetic-storm-levels-reached-19-jan-2026
499•WorldPeas•17h ago•164 comments

Increasing the performance of WebAssembly Text Format parser by 350%

https://blog.gplane.win/posts/improve-wat-parser-perf.html
51•gplane•5d ago•21 comments

Reticulum, a secure and anonymous mesh networking stack

https://github.com/markqvist/Reticulum
244•brogu•13h ago•53 comments

Apple testing new App Store design that blurs the line between ads and results

https://9to5mac.com/2026/01/16/iphone-apple-app-store-search-results-ads-new-design/
437•ksec•20h ago•351 comments

IP over Avian Carriers with Quality of Service (1999)

https://www.rfc-editor.org/rfc/rfc2549.html
15•mig4ng•2h ago•6 comments

Channel3 (YC S25) Is Hiring

https://www.ycombinator.com/companies/channel3/jobs/3DIAYYY-backend-engineer
1•aschiff1•1h ago

The Overcomplexity of the Shadcn Radio Button

https://paulmakeswebsites.com/writing/shadcn-radio-button/
366•dbushell•5h ago•194 comments

What came first: the CNAME or the A record?

https://blog.cloudflare.com/cname-a-record-order-dns-standards/
387•linolevan•20h ago•139 comments

x86 prefixes and escape opcodes flowchart

https://soc.me/interfaces/x86-prefixes-and-escape-opcodes-flowchart.html
72•gaul•9h ago•23 comments

Nanolang: A tiny experimental language designed to be targeted by coding LLMs

https://github.com/jordanhubbard/nanolang
177•Scramblejams•15h ago•134 comments

String theory can now describe a universe that has dark energy?

https://www.quantamagazine.org/string-theory-can-now-describe-a-universe-that-has-dark-energy-202...
44•nsoonhui•3h ago•32 comments

The coming industrialisation of exploit generation with LLMs

https://sean.heelan.io/2026/01/18/on-the-coming-industrialisation-of-exploit-generation-with-llms/
175•long•1d ago•121 comments

Benchmarking a Baseline Fully-in-Place Functional Language Compiler [pdf]

https://trendsfp.github.io/papers/tfp26-paper-12.pdf
5•matt_d•3d ago•0 comments

Notes on Apple's Nano Texture (2025)

https://jon.bo/posts/nano-texture/
204•dsr12•19h ago•108 comments

Scaling long-running autonomous coding

https://simonwillison.net/2026/Jan/19/scaling-long-running-autonomous-coding/
119•srameshc•13h ago•52 comments

3D printing my laptop ergonomic setup

https://www.ntietz.com/blog/3d-printing-my-laptop-ergonomic-setup/
89•kurinikku•13h ago•24 comments

Giving university exams in the age of chatbots

https://ploum.net/2026-01-19-exam-with-chatbots.html
146•ploum•5h ago•91 comments

Prediction markets are ushering in a world in which news becomes about gambling

https://www.theatlantic.com/technology/2026/01/america-polymarket-disaster/685662/
323•krustyburger•1d ago•333 comments

British redcoat's lost memoir reveals realities of life as a disabled veteran

https://phys.org/news/2026-01-british-redcoat-lost-memoir-reveals.html
97•wglb•4d ago•97 comments

Kahan on the 8087 and designing Intel's floating point (2016) [video]

https://www.youtube.com/watch?v=L-QVgbdt_qg
34•bananaboy•5d ago•1 comments

Nova Launcher added Facebook and Google Ads tracking

https://lemdro.id/post/lemdro.id/35049920
294•celsoazevedo•12h ago•138 comments

Porsche sold more electrified cars in Europe in 2025 than pure gas-powered cars

https://newsroom.porsche.com/en/2026/company/porsche-deliveries-2025-41516.html
359•m463•12h ago•468 comments

Targeted Bets: An alternative approach to the job hunt

https://www.seanmuirhead.com/blog/targeted-bets
82•seany62•15h ago•76 comments

The microstructure of wealth transfer in prediction markets

https://www.jbecker.dev/research/prediction-market-microstructure
175•jonbecker•21h ago•157 comments

The assistant axis: situating and stabilizing the character of LLMs

https://www.anthropic.com/research/assistant-axis
105•mfiguiere•16h ago•17 comments

Understanding ZFS Scrubs and Data Integrity

https://klarasystems.com/articles/understanding-zfs-scrubs-and-data-integrity/
61•zdw•5d ago•30 comments

From Nevada to Kansas by Glider

https://www.weglide.org/flight/978820
154•sammelaugust•4d ago•49 comments
Open in hackernews

How ZGC allocates memory for the Java heap

https://joelsiks.com/posts/zgc-heap-memory-allocation/
86•lichtenberger•9mo ago

Comments

gopalv•9mo ago
The 32x virtual memory to physical memory ratio plays into relocation and colored pointers (i.e pointers where some bits serve as flag bits).

Putting the actual data layouts in 44 bits out of 64 is a neat trick which relies on the allocator being aware of the mappings between physical and virtual addresses.

twoodfin•9mo ago
When your comment and the article refer to “physical” addresses, those are physical in the context of the JVM, right? To the OS they’re virtual addresses in the JVM process space?
acchow•9mo ago
Correct. ZGC has no way to escape from the virtualization by the kernel (assuming your hardware and kernel uses an MMU)
MBCook•9mo ago
Thank you for the answer, I was wondering that as well.
hinkley•9mo ago
In the beginning of the 32 bit revolution, when the future was here but unevenly distributed, there was a lot of talk about how 32 bit pointers would fundamentally change how people wrote code. Among other things it got rid of a bunch of odd bookkeeping, and if you don’t have to do the bookkeeping you don’t have to write the code in a way that supports it, so you can do other things.

Not too long after someone asked what sort of interesting changes 64 bit will bring. And I’ve been keeping that question in the back of my mind ever since.

Aliasing memory multiple times in order to do read or write barriers and make GC much cheaper is a pretty good one. But another one I know of is that one of the secrets of the L4 microkernel is that its IPC speed comes substantially from reducing the amount of TLB work that needs to be done to switch to another process running in a different address space. They use the same address space and only swap out the access rights which cuts the call overhead in half. It’s pretty easy to put a bunch of processes into a 64 bit address space and just throw each one a randomly located 4GB slice of RAM.

twoodfin•9mo ago
Yeah, would love to see the CPU vendors invent some primitives to let user code pull those kinds of privilege isolation tricks within a single process and address space.

Something like: “From now on, code on these pages can only access data on these pages, and only return to/call into other code through these gates…”

hinkley•9mo ago
Thread based seems like it at least should be possible.
ahartmetz•9mo ago
I've had some ideas about avoiding format validation in IPC receivers if the data is encoded by trusted code, which is also the only code that has rights to send the IPC data / to connect to the receiver. I can't really think of an important problem that it would solve, though. DBus always validates received data, but it's not really meant or very suitable for large amounts of data anyway.
twoodfin•9mo ago
What I’m looking for is a way for a process to de/re-escalate its privileges to access memory, without an expensive context switch being required at the transition. The CPU would simply enforce different rules based on (say) the high-order bits of the instruction pointer.

Imagine a server process that wants to run some elaborate third-party content parser. It’d be great to be sure that no matter how buggy or malicious that code, it can’t leak the TLS keys.

Today, high-security architectures must use process isolation to achieve this kind of architectural guarantee, but even finely tuned IPC like L4’s is an order of magnitude slower than a predictable jump.

gpderetta•9mo ago
For a brief moment Intel supported MPX which did something similar.

You can also play tricks with the virtualization hardware, bit it need kernel support.

Eventually we will get segments back again.

MarkSweep•9mo ago
That would be pretty cool. Something like the Win32 function GetWriteWatch, but implemented in hardware instead of the page fault handler (I assume).

https://learn.microsoft.com/en-us/windows/win32/api/memoryap...

Or some sort of special write barrier store op-code, idk.

mike_hearn•9mo ago
It exists, that's called MPKs.
twoodfin•9mo ago
I don’t think MPK’s will fit the need I have. Simply: Run some arbitrary, untrusted, non-sandboxed code in the same thread with assurance it can’t read page X. When that code completes and I’m back in code I trust, X is readable again.

Is that something MPK makes possible? The doc I’ve read suggests either your process can flip permission bits or it can’t. Great for avoiding out-of-sandbox reads. But if there’s arbitrary execution happening, why can’t that code flip the access to secrets back on?

mike_hearn•8mo ago
Oracle Labs has tech that does that:

https://youtu.be/T05FI93MBI8?si=EieFgujaGiW2gbO8&t=958

The trick is to do a cascading disassembly of all untrusted code you'll execute to prove it can't change the MPK register.

twoodfin•8mo ago
Wow. Neat trick and exactly the kind of thing I was looking for.

Thanks!

EDIT: Looks like this is the relevant paper from the Graal team: https://www.graalvm.org/resources/articles/binsweep.pdf

jdougan•9mo ago
Is that something like the memory protection scheme on the Newton OS?
nyanpasu64•9mo ago
Isn't not swapping page tables during a call precisely what the KPTI mitigations had to turn off for Meltdown mitigations?
pron•9mo ago
For relevant upcoming changes see Automatic Heap Sizing for ZGC: https://openjdk.org/jeps/8329758