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Astra for Law

https://openai.com/index/astra-for-law/
272•vertigoruntime•4h ago•306 comments

Bonsai 2 27B: Near-Lossless Compression in a 9x Smaller Footprint

https://prismml.com/news/bonsai-2-27b
169•JonSchneider•3h ago•55 comments

Bend – A language that blocks AI mistakes via proof, on CPU and GPU

https://bend-lang.com/
245•nicolas-siplis•4h ago•130 comments

Hister: A private search engine for the pages you visit and the files you keep

https://github.com/asciimoo/hister
433•bookofjoe•8h ago•130 comments

Wax motor

https://en.wikipedia.org/wiki/Wax_motor
215•mhb•1d ago•42 comments

Fujitsu launches made-in-Japan next-generation CPU FUJITSU-MONAKA

https://global.fujitsu/en-global/pr/news/2026/09/14-02
495•my123•2d ago•191 comments

More than 100k people in Japan are now aged 100 or older

https://www.bbc.com/news/articles/cmzezj5e18xxo
75•karakoram•4h ago•55 comments

Flet 1.0 – Build cross-platform apps in Python

https://flet.dev/
46•absqueued•3h ago•16 comments

Diplodocus, Long Thought Exclusively American, Turns Up in Spain

https://www.sci.news/paleontology/spanish-diplodocus-15064.html
23•embedding-shape•2d ago•15 comments

CrowdSec Source Code Leak

https://www.crowdsec.net/blog/crowdsec-statement-source-code-exposure
127•eccgecko•9h ago•35 comments

Landing the Space Shuttle – A Flying Machine and the Thrill of a Lifetime

https://inspire.eaa.org/2019/05/16/landing-the-space-shuttle-an-incredible-flying-machine-and-the...
13•JojoFatsani•1d ago•2 comments

Rate limits on GitLab.com are changing

https://about.gitlab.com/blog/rate-limit-change-2026/
146•darkwater•9h ago•105 comments

Infinite-Parameter LLMs: Generating and Adapting Weights from Live Data

https://arxiv.org/abs/2609.18842
104•Betelbuddy•7h ago•29 comments

How GLM built its own inference infrastructure

https://z.ai/blog/glm-built-its-inference-infrastructure
371•whiteros_e•16h ago•260 comments

How Uber Protects Against Retry Storms

https://www.uber.com/us/en/blog/protecting-against-retry-storms/
28•iscmt•3h ago•16 comments

Why I didn’t sign the Fields medallists’ letter

https://gowers.wordpress.com/2026/09/17/why-i-didnt-sign-the-fields-medallists-letter/
196•simianwords•15h ago•278 comments

TSMC revealing details about next gen A14 node

https://iedm26.mapyourshow.com/8_0/sessions/session-details.cfm?scheduleid=331
86•osnium123•2d ago•32 comments

How do we prevent mathemathics from devolving into the Medieval Era of secrecy?

https://mathoverflow.net/questions/515260/how-do-we-prevent-mathematics-from-devolving-into-the-m...
67•jjgreen•2d ago•46 comments

The American Religion of Self-Storage Facilities

https://www.newyorker.com/magazine/2026/09/21/the-american-religion-of-self-storage-facilities
183•pseudolus•11h ago•321 comments

CCC invites all model citizens to 40C3

https://events.ccc.de/en/2026/09/12/40c3-model-citizens/
328•antonly•16h ago•178 comments

Zettascale (YC S24) Is Hiring ASIC/FPGA Engineers to Build Chips for ASI

https://zscc.ai/careers?job_id=109821
1•el_al•7h ago

Plugin4Shell – Zero Click RCE Vulnerability found in top four coding agents

https://www.air.security/blog-posts/plugin4shell
4•fishthethis•4h ago•2 comments

The most important product decision is what you don't build

https://liamnugent.me/posts/what-you-dont-build/
32•ChrisArchitect•3h ago•14 comments

Running Ubuntu on the Lenovo IdeaPad Duet

https://vhaudiquet.fr/blog/duet-ubuntu/
62•vhaudiquet•3d ago•23 comments

Show HN: Snapdrop: Instantly share files between devices. No setup, no signup

https://snapdrop.me
15•Capira•3h ago•12 comments

Launch HN: Skillsync (YC W26) – AI chat sessions made portable across agents

44•cat-whisperer•8h ago•46 comments

Show HN: Share your AI Setup, Learn from others

https://mysetup.ai/
176•steveybrown•11h ago•89 comments

André Weil and the Hodge Conjecture

https://jiahao116.github.io/Articles/
29•caojiahao•5d ago•10 comments

My temporary PHP fix from 2014 has nearly 20M installs. Today I'm deprecating it

https://jakeasmith.com/blog/http-build-url/
323•jakeasmith•2d ago•96 comments

Sex, AI, and the Apocalypse

https://www.iankduncan.com/personal/2026-09-16-sex-ai-and-the-apocalypse/
134•Anon84•3h ago•114 comments
Open in hackernews

How ZGC allocates memory for the Java heap

https://joelsiks.com/posts/zgc-heap-memory-allocation/
86•lichtenberger•1y ago

Comments

gopalv•1y ago
The 32x virtual memory to physical memory ratio plays into relocation and colored pointers (i.e pointers where some bits serve as flag bits).

Putting the actual data layouts in 44 bits out of 64 is a neat trick which relies on the allocator being aware of the mappings between physical and virtual addresses.

twoodfin•1y ago
When your comment and the article refer to “physical” addresses, those are physical in the context of the JVM, right? To the OS they’re virtual addresses in the JVM process space?
acchow•1y ago
Correct. ZGC has no way to escape from the virtualization by the kernel (assuming your hardware and kernel uses an MMU)
MBCook•1y ago
Thank you for the answer, I was wondering that as well.
hinkley•1y ago
In the beginning of the 32 bit revolution, when the future was here but unevenly distributed, there was a lot of talk about how 32 bit pointers would fundamentally change how people wrote code. Among other things it got rid of a bunch of odd bookkeeping, and if you don’t have to do the bookkeeping you don’t have to write the code in a way that supports it, so you can do other things.

Not too long after someone asked what sort of interesting changes 64 bit will bring. And I’ve been keeping that question in the back of my mind ever since.

Aliasing memory multiple times in order to do read or write barriers and make GC much cheaper is a pretty good one. But another one I know of is that one of the secrets of the L4 microkernel is that its IPC speed comes substantially from reducing the amount of TLB work that needs to be done to switch to another process running in a different address space. They use the same address space and only swap out the access rights which cuts the call overhead in half. It’s pretty easy to put a bunch of processes into a 64 bit address space and just throw each one a randomly located 4GB slice of RAM.

twoodfin•1y ago
Yeah, would love to see the CPU vendors invent some primitives to let user code pull those kinds of privilege isolation tricks within a single process and address space.

Something like: “From now on, code on these pages can only access data on these pages, and only return to/call into other code through these gates…”

hinkley•1y ago
Thread based seems like it at least should be possible.
ahartmetz•1y ago
I've had some ideas about avoiding format validation in IPC receivers if the data is encoded by trusted code, which is also the only code that has rights to send the IPC data / to connect to the receiver. I can't really think of an important problem that it would solve, though. DBus always validates received data, but it's not really meant or very suitable for large amounts of data anyway.
pron•1y ago
For relevant upcoming changes see Automatic Heap Sizing for ZGC: https://openjdk.org/jeps/8329758
twoodfin•1y ago
What I’m looking for is a way for a process to de/re-escalate its privileges to access memory, without an expensive context switch being required at the transition. The CPU would simply enforce different rules based on (say) the high-order bits of the instruction pointer.

Imagine a server process that wants to run some elaborate third-party content parser. It’d be great to be sure that no matter how buggy or malicious that code, it can’t leak the TLS keys.

Today, high-security architectures must use process isolation to achieve this kind of architectural guarantee, but even finely tuned IPC like L4’s is an order of magnitude slower than a predictable jump.

gpderetta•1y ago
For a brief moment Intel supported MPX which did something similar.

You can also play tricks with the virtualization hardware, bit it need kernel support.

Eventually we will get segments back again.

MarkSweep•1y ago
That would be pretty cool. Something like the Win32 function GetWriteWatch, but implemented in hardware instead of the page fault handler (I assume).

https://learn.microsoft.com/en-us/windows/win32/api/memoryap...

Or some sort of special write barrier store op-code, idk.

mike_hearn•1y ago
It exists, that's called MPKs.
twoodfin•1y ago
I don’t think MPK’s will fit the need I have. Simply: Run some arbitrary, untrusted, non-sandboxed code in the same thread with assurance it can’t read page X. When that code completes and I’m back in code I trust, X is readable again.

Is that something MPK makes possible? The doc I’ve read suggests either your process can flip permission bits or it can’t. Great for avoiding out-of-sandbox reads. But if there’s arbitrary execution happening, why can’t that code flip the access to secrets back on?

mike_hearn•1y ago
Oracle Labs has tech that does that:

https://youtu.be/T05FI93MBI8?si=EieFgujaGiW2gbO8&t=958

The trick is to do a cascading disassembly of all untrusted code you'll execute to prove it can't change the MPK register.

twoodfin•1y ago
Wow. Neat trick and exactly the kind of thing I was looking for.

Thanks!

EDIT: Looks like this is the relevant paper from the Graal team: https://www.graalvm.org/resources/articles/binsweep.pdf

jdougan•1y ago
Is that something like the memory protection scheme on the Newton OS?
nyanpasu64•1y ago
Isn't not swapping page tables during a call precisely what the KPTI mitigations had to turn off for Meltdown mitigations?