> The CPU (the Motorola 68000) initiates all communication in the case of the Macintosh
Minor nitpick but the video controller has direct access to RAM and when the visible part of the display is being drawn by the video controller, it does cycle-stealing DMA that preempts the CPU.
You can read in depth about it from Steve Chamberlain, the designer of an FPGA low level clone of the Mac Plus here: [0]
By the way but this why the compact Macs have CPU performance of about a 6 MHz 68000 when clocked at almost 8 MHz. About half the time the display is being redrawn. And about half the memory bandwidth is used up at those times.
Bit of a tangent but the Apple II used a similar approach for its video system. As the article notes, the 68K has a prefetch queue. So it's always reading ahead which is what you get from reading an open bus. But the 6502 is a simple CPU without that fancy prefetch queue, so if you read a non-extant address on the Apple II you get what the video system just read and drew in the previous half-cycle. It's possible to sync up the CPU with the video system this way; something otherwise impossible on the Apple II. [1]
> Bit of a tangent but the Apple II used a similar approach for its video system.
A lot of home computers did. The ZX Spectrum has the same weirdass screen layout as Apple II HGR, for much the same reason - the screen is scanned in 256-byte (32 bytes by eight rows) blocks so that you hit all the 256 byte pages with a refresh one after the other. It's kind of an odd choice because the Z80 could be set up to handle DRAM refresh by itself, but the 6502 did not have that luxury.
retrac•2mo ago
Minor nitpick but the video controller has direct access to RAM and when the visible part of the display is being drawn by the video controller, it does cycle-stealing DMA that preempts the CPU.
You can read in depth about it from Steve Chamberlain, the designer of an FPGA low level clone of the Mac Plus here: [0]
By the way but this why the compact Macs have CPU performance of about a 6 MHz 68000 when clocked at almost 8 MHz. About half the time the display is being redrawn. And about half the memory bandwidth is used up at those times.
Bit of a tangent but the Apple II used a similar approach for its video system. As the article notes, the 68K has a prefetch queue. So it's always reading ahead which is what you get from reading an open bus. But the 6502 is a simple CPU without that fancy prefetch queue, so if you read a non-extant address on the Apple II you get what the video system just read and drew in the previous half-cycle. It's possible to sync up the CPU with the video system this way; something otherwise impossible on the Apple II. [1]
[0] https://www.bigmessowires.com/2011/08/25/68000-interleaved-m...
[1] http://www.deater.net/weave/vmwprod/megademo/vapor_lock.html
ErroneousBosh•2mo ago
A lot of home computers did. The ZX Spectrum has the same weirdass screen layout as Apple II HGR, for much the same reason - the screen is scanned in 256-byte (32 bytes by eight rows) blocks so that you hit all the 256 byte pages with a refresh one after the other. It's kind of an odd choice because the Z80 could be set up to handle DRAM refresh by itself, but the 6502 did not have that luxury.