For a second, I thought the headline was copied & pasted from the hallucinated 10-years-from-now HN frontpage that recently made the HN front page:
Memristors are also probably coming after MRAM-CIM and before photonic computing.
Specifically this paper is based on simulations, and I've only skimmed the paper, but the power efficiency numbers sound great because they say 40 GHz read/write speeds, but these consume comparatively large powers even if not reading or writing (the lasers have to be running constantly). I also think they did not include the contributions of the modulation and the required drivers (typically you need quite large voltages)? Somebody already pointed out that the size of these is massive, and that's again fundamental.
As someone working in the broad field, I really wish people would stop these type of publications. While these numbers might sound impressive at a first glance, they really are completely unrealistic. There are lots of legitimate applications of optics and photonics, we don't need to resort to this sort of stuff.
> they really are completely unrealistic
Unrealistic only because they're power hungry? That sounds like a temporary problem, kind of like when we come up with a bunch of ML approaches we couldn't actually do in the 80s/90s because of the hardware resources required, but today work fine.
Maybe even if the solution aren't useful today, they could be useful in the future? Or maybe with these results, there are more people being inspired to create solutions specifically about the power usage?
"we don't need to resort to this sort of stuff" makes it sound like this is all so beneath you and not deserving of attention, but why are you then paying attention to it?
There are promising avenues to use "bosonic" nonlinearity to overtake traditional fermionic computing, but they are basically not being explored by EE departments despite (because of?) their oversized funding and attention
No they are fundamentally power hungry because you essentially need a nonlinear response, i.e. photons need to interact with each other. However photons are bosons and really dislike interacting with each other.
Same thing about the size of the circuits they are determined by the wavelength of light, so fundamentally they are much larger than electronic circuits.
> "we don't need to resort to this sort of stuff" makes it sound like this is all so beneath you and not deserving of attention, but why are you then paying attention to it?
That's not what I said, in fact they deserve my attention because they need to be called out, as the article clearly does not highlight the limitations.
The core section from paper (linked below) is pp8-9.
2mW for 100s of picosecs is huge.
(Also GIANT voltages,if only to illustrate how coarse their simulations are):
As shown in Figure 6(a), even with up to 1 V of noise on each Q and QB node (resulting in a 2 V differential between Q and QB), the pSRAM bitcell successfully regenerates the previously stored data. It is important to note that higher noise voltages increase the time required to restore the original state, but the bitcell continues to function correctly due to its regenerative behavior.
We are going tohave energy abundant at some point.
https://arxiv.org/abs/2503.19544v1
The memory cell is huge in comparison with semiconductor memories, but it is very fast, with a 40 GHz read/write speed.
There are important applications for a very high speed small memory, e.g. for digital signal processing in radars and other such devices, but this will never replace a general-purpose computer memory, where much higher bit densities are needed.
Nice AI text again
lebuffon•1mo ago
(I am sure they meant nm, but nobody is checking the AI output)
vlovich123•1mo ago
> footprint of 330 × 290 µm2 using the GlobalFoundries 45SPCLO
That’s a 45nm process but the units for the chip size probably should have been 330um? However I’m not well versed enough in the details to parse it out.
https://arxiv.org/abs/2503.19544
bgnn•1mo ago
The area is massive. 330um × 290um are the X and Y dimensions. The area is roughly 0.1 mm2. You can see the comparison on table 1. This is roughly 50000 times larger than an SRAM of 45nm process.
This is the problem with photonic circuits. They are massive compared to electronics.
bun_at_work•1mo ago
adrian_b•1mo ago
This is why modern semiconductor devices no longer use lithography with visible light or even with near ultraviolet, but they must use extreme ultraviolet.
The advantage of such optical devices is speed and low power consumption in the optical device itself (ignoring the power consumption of lasers, which might be shared by many devices).
Such memories have special purposes in various instruments, they are not suitable as computer memories.
bgnn•1mo ago
To give a feeling: micro-ribg resonators are anywhere between 10 to 40 micrometer in diameter. You also need a bunch of other waveguides. The process in the paper uses silicon waveguides, with 400nm width if I'm not wrong. So any optical feature unfortunately isn't going down as much as CMOS technology.
Fun fact: the photolithography has the same limitations. They use all kinds of tricks (different optical affects to shrink the features) but fundamentally limited by the wavelength used. This is why we are seeing a push to a lower and lower wavelengths by ASML. That + multiple patterning helps to scale CMOS down.
pezezin•1mo ago
bgnn•1mo ago
pezezin•1mo ago
KK7NIL•1mo ago
The text in the article supports this:
> This is a commercial 300mm monolithic silicon photonics platform, meaning the technology is ready to scale today, rather than being limited to laboratory experiments.