AMD's Ryzen 9 9950X3D2 Dual Edition crams 208MB of cache into a single chip

https://arstechnica.com/gadgets/2026/03/amds-ryzen-9-9950x3d2-dual-edition-crams-208mb-of-cache-into-a-single-chip/

56•zdw•2h ago

Comments

Readerium•1h ago

Can someone explain if the 3D Vcache are stacked on top of each other or side by side.

If they are stacked then why not 9800X3D2?

zdw•1h ago

The 99xx chips have two CPU dies, and one cache die is on each CPU die.

modeswitch•49m ago

The 3D V-Cache sits underneath only one of the CCDs. See https://en.wikipedia.org/wiki/Ryzen#Ryzen_9000.

Tostino•31m ago

Did you forget which thread we are on?

anonymars•8m ago

That's what's different about this one. "Enter the Ryzen 9 9950X3D2 Dual Edition, a mouthful of a chip that includes 64MB of 3D V-Cache on both processor dies, without the hybrid arrangement that has defined the other chips up until now."

trynumber9•35m ago

It is 2 separate cache dies bonded to 2 separate compute dies which in turn maintain coherency and access memory via Infinity Fabric in the single IO die.

chao-•1h ago

Crazy to think that my first personal computer's entire storage (was 160MB IIRC?) could fit into the L3 of a single consumer CPU!

It's probably not possible architecturally, but it would be amusing to see an entire early 90's OS running entirely in the CPU's cache.

bombcar•1h ago

IIRC some relatively strange CPUs could run with unbacked cache.

twbarr•1h ago

Intel's platform, at the very least, use cache-as-ram during the boot phase before the DDR interface can be trained and started up. https://github.com/coreboot/coreboot/blob/main/src/soc/intel...

cwzwarich•1h ago

https://github.com/coreboot/coreboot/blob/main/src/soc/intel...

wmf•24m ago

Context: Early in the firmware boot process the memory controller isn't configured yet so the firmware uses the cache as RAM. In this mode cache lines are never evicted since there's no memory to evict them to.

pwg•49m ago

In my case it began with 16K (yes, 161024 bytes) and 90K (yes, 901024 bytes) 5.25" floppy disks (although the floppies were a few months after the computer). Eventually upgraded to 48K RAM and 180K double density floppy disks. The computer: Atari 800.

MegaDeKay•35m ago

I'll see your Atari 800 and raise you my Atari 2600 with its whopping 128 bytes of RAM. Bytes with a B. I can kinda sorta call it a computer because you could buy a BASIC cartridge for it (I didn't and stand by that decision - it was pretty bad).

basilikum•46m ago

KolibriOS would fit in there, even with the data in memory. You cannot load it into the cache directly, but when the cache capacity is larger than all the data you read there should be no cache eviction and the OS and all data should end up in the cache more or less entirely. In other words it should be really, really fast, which KolibriOS already is to begin with.

vlovich123•43m ago

Unless you lay everything out continuously in memory, you’ll still get cache eviction due to associativty and depending on the eviction strategy of the CPU. But certainly DOS or even early Windows 95 could conceivably just run out of the cache

basilikum•39m ago

Well, yeah, reality strikes again. All you need is an exploit in the microcode to gain access to AMD's equivalent to the ME and now you can just map the cache as memory directly. Maybe. Can microcode do this or is there still hardware that cannot be overcome by the black magic of CPU microcode?

chao-•37m ago

Yeah, cache eviction is the reason I was assuming it is "probably not possible architecturally", but I also figured there could be features beyond my knowledge that might make it possible.

Edit: Also this 192MB of L3 is spread across two Zen CCDs, so it's not as simple as "throw it all in L3" either, because any given core would only have access to half of that.

m463•43m ago

I wonder how much faster dos would boot, especially with floppy seek times...

userbinator•41m ago

Instantly.

If you run a VM on a CPU like this, using a baremetal hypervisor, you can get very close to "everything in cache".

renewiltord•57m ago

I have a gigabyte of cache on my 9684x at home!

nexle•38m ago

Breakdown of the (semi-clickbait) 208MB cache: 16MB L2 (8MB per die?) + 32MB L3 * 2 dies + 64MB L3 Stacked 3D V-cache * 2

For comparison, 9950X3D have a total cache of 144MB.

trynumber9•29m ago

> 16MB L2 (8MB per die?)

It is indeed 8MB per compute die but really 1MB per core. Not shared among the entire CCD.

magicalhippo•20m ago

Probably fun for those who already bought DDR5 memory... still kicking myself for not just pulling the trigger on that 128GB dual stick kit I looked at for $600 back in September. Now it's listed at $4k...

Meanwhile I hope my AM4 will chug along a few more years.

fc417fc802•13m ago

Given that the dies still have L3 on them does this count as L4 or does the hardware treat it as a single pool of L3?

Would be neat to have an additional cache layer of ~1 GB of HBM on the package but I guess there's no way that happens in the consumer space any time soon.

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AMD's Ryzen 9 9950X3D2 Dual Edition crams 208MB of cache into a single chip

Comments

Don't YOLO your file system

AMD's Ryzen 9 9950X3D2 Dual Edition crams 208MB of cache into a single chip

Make macOS consistently bad unironically

LG's new 1Hz display is the secret behind a new laptop's battery life

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