Consider me educated on the mantissa. That's a nifty pedantry.
Typo in the c++?
> cout << "x =/= x: " << ((x=x) ? "true" : "false") << endl;
Should be x != x?
For the leading 0 counter, I've found it's even better for the tool if I use a for loop. Keeps things scalable and it's even less code. I'm not understanding this takeaway though
> Sometimes a good design is about more than just performance.
The good design (unless the author's note that it's easier to read and maintain makes it worse design?) was better performing. So sometimes a good design creates performance.
Likewise for pipelining: it would have been interesting to know if the tools can reorder operations if you give them some pipeline registers to play with. In Xilinx land it'll move your logic around and utilize the flops as it sees fit.
Taniwha•1h ago
CyLith•1h ago
adgjlsfhk1•17m ago
trollbridge•18m ago