I've been playing with makerlisp.com's COR24-TB 24-bit RISC soft CPU development board. I developed a Rust emulator for this ISA. The Rust emulator can run inside of a Yew/WASM app in the browser. The TUI is an ncurses-inspired variable tiled window panes. The O/S supports preemptive multitasking. There are cpu-hogs that do not yield that are force preempted. You can run interactive apps and background apps. It has a shell, monitor, debugger, and a few bundled apps.

I plan to add an SPI SD card to load programs. It currently supports up to 16 processes (sharing 1M RAM, no MMU, no internal clock, and I2C clock to be added). Right now, the modified terminal emulator (and WASM demo) send clocks to the O/S which drives the UART ISR to do the cooperative (and when needed, the preemptive) dispatching.

I developed this using a language I built that was inspired by PL/M and IBM's PL/I (PL/AS, PL/X) languages (because I wanted metaprogramming via executable macros).

I've developed many compilers and interpreters that run on COR24 ISA (not yet in this demo; they have their own demos). I plan to port a lot of this work to ARM and RISC dev boards with NPUs to explore edge ML.

Sorry, this was supposed to be a Show HN: post. Too late for me to edit the title. Maybe I will resubmit correctly in the future.