Finally finished my little CPU project, RISCY-V02. I built it (with Claude) to challenge the notion that the 6502 was a "local optimum" in its transistor budget. Given the constraints of 1970s home computers (~1 MHz DRAM, so raw clock speed doesn't help), could RISC have been a better design choice? This design argues yes: pipelining, barrel shifters, and more registers beat microcode PLAs, questionable addressing modes, and hardware BCD.

Highlights:

8x 16-bit general-purpose registers (vs 3x 8-bit on 6502)

2-stage pipeline (Fetch/Execute) with speculative fetch

61 fixed 16-bit instructions

2-cycle interrupt entry (vs 7 on 6502)

13,844 SRAM-adjusted transistors (vs 13,176 for 6502 on same process)

1.0-2.6x faster than 6502 across common routines

GDS viewer: https://mysterymath.github.io/riscyv02-sky

Tiny Tapeout Shuttle Entry: https://app.tinytapeout.com/projects/3829