We’ve been building an open-source FPGA-based 400G RDMA-like SmartNIC called OpenRDMA.

The project includes RTL, drivers, and the FPGA data path implementation. Current hardware throughput has reached around 200Gbps so far.

One interesting aspect has been verification: we’ve been using LLM-generated cocotb testbenches quite extensively. AI is still weak at SystemVerilog, but surprisingly useful for Python-based cocotb verification workflows.

The entire stack is open-source: github.com/open-rdma/open-rdma

Would love feedback from people working on FPGA networking, RDMA, SmartNICs, or high-performance infrastructure.