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Show HN: A Project Oberon System version running on RISC-V instead of RISC-5

https://github.com/rochus-keller/OberonSystem/tree/op2-rv32
22•Rochus•1h ago

Comments

OCTAGRAM•29m ago
> The whole system runs on a low-cost development board (Xilinx Spartan-3 by Digilent, with 1 MB of static RAM)

If somebody wants their FPGA work to be available, they better choose MiSTer FPGA from the beginning. Costlier, but way more likely to be found around.

Rochus•17m ago
The availability of the board to run Wirt's system was an issue pretty soon. There were even people who offered their own boards to fill the gap (e.g. https://web.archive.org/web/20160831063355/http://oberonstat...).

My system version instead runs on RISC-V, so no custom FPGA implementation, currently on an emulator, but eventually on the ESP32 (which has a much better availability).

Joker_vD•11m ago
> they better choose MiSTer FPGA from the beginning.

Well, the MiSTer project was yet 4 years from being launched back in 2013 when the RISC-5 was implemented in FPGA, so I hope you'd excuse Wirth from not choosing it.

Show HN: A Project Oberon System version running on RISC-V instead of RISC-5

https://github.com/rochus-keller/OberonSystem/tree/op2-rv32
23•Rochus•1h ago•3 comments

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