> The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
While it would be nice to have more elegant support for "modern" codegen in the sv/verilog/vhdl, the real unergonomic experiences are test bench design and integration. The only real options are (for sv, verilog, I have less experience with vhdl): use verilator and write your tb in cpp, use verilator and then write your testbench in cocotb, or you work at a chip design company and use one of the big 3's compilers and maybe you use UVM or cocotb. Verilator and cocotb are okay, but you're crossing a language boundar(ies) and referencing generated code -- it is both mechanical and complex to get any design working with it.
If sus had first class interfaces to create testbenches that could map to UVM or verilator, it would be much more interesting. Spade does some interesting things by having its own package manager, but doesn't (afaik) expose a ton within the language itself
We are so stupidly limited by our EDA tooling and infrastructure. I wish these efforts would have been put to use in that front.
The problem that no one will ever solve is there's no gcc equivalent to NXT. Everything is downstream of that problem.
go back in time to before gcc - i'm 100% sure people were saying the exact same thing about borland (or whatever).
A sufficiently smart compiler requires ever more clever compiler writers who are deeply knowledgeable about the many quirks of the numerous architectures.
Intel's compiler are clang forks.
But even when using plain verilog the language was never the limiting factor on the design process.
SUS ? Single UNIX Specification ?
randomNumber7•7mo ago