Not to take away from this cool project, but its design decisions are incredibly impractical.

> It isn't just a reimplementation of existing software logic in hardware; it is a rethinking of how deep learning inference should work at the circuit level. [...] By implementing the entire inference pipeline in SystemVerilog, we achieve deterministic, cycle-accurate control over every calculation. [...] But don’t let the two-week timeline fool you. Those were two weeks full of 18-hour days, fueled by caffeine and sheer stubbornness.

I'm having a hard time figuring out if this is satire or not.

My advice: write your own English prose, and try not to let "LLM-speak" leak into your documentation when using them to edit. Ironically, LLMs just plain suck at writing English, like they're incredibly overfit on marketing copy and press releases. I hope someone is working on this, or at least cares about the problem, because that would make this brave new world palatable for reading.

This is horrible LLM slop, my god.

Winced my way through “Convolutions are in CNNs (it’s literally in the name, Convolutional Neural Network)”, then had to stop.

It’s honestly offensive to me. It doesn’t even make sense on its own terms. For some reason we fly from LLM inferencing to toy MSINT to convolutions with __0__ transition or sense of structure.

If the author and/or anyone else hasn't seen Sidero's Talos Linux distro, it's my current favorite way to spin up a bare metal Kubernetes cluster:

https://www.talos.dev/

> Talos is a custom FPGA-based hardware accelerator built from the ground up to execute Convolutional Neural Networks with extreme efficiency

Makes it sound like it's new hardware. This is just (I'm inferring) software to program an off the shelf FPGA to do convolutions. Very minimal ones by the look of it (MNIST etc).