The PS3 was used a few time in clusters – some NN work was done on it back in the day. My understanding (somewhat echoed in TFA) is that when programming Cell, you really needed to think about communication patterns to avoid quickly running into memory bandwidth limitations, especially given memory hierarchy and bus quirks.

https://open.clemson.edu/all_theses/629/

Eugh, maybe?

The PS3 only had 256mb of main memory so you'd be pretty limited there. Memory bandwidth, great at the time, is pretty poor by today's standards (25 gb/s)

It's a nearly 20 year old gaming console. Even if you could port a deep learning workload to run efficiently on the Cell architecture, it would be thoroughly outclassed by a modern cell phone (to say nothing of a desktop computer).

With enough effort you could definitely do it. Just remember it is a device that came out in 2006 and it has 256MB of system RAM and 256MB of VRAM, at best you're running a quite small model after a lot work trying to port some inference code to CELL processors. Honestly it does sound a cool excuse to write code for the CELL processors, but don't expect amazing performance or anything.

Please see this: https://github.com/flipacholas/Architecture-of-consoles

> A suggestion from me is to provide sources, and also maybe an epub of this

What do you mean?

The EIB has nothing to do with 1980s Token Ring and this is arguably a mistake in the article. It's just a ring topology.

Sounds like a Gantt chart with code might fit.

That would be the PS2’s VUs which had an upper and lower pipe and it was easier to write instructions for each in separate columns. Then in one SDK we received program called vcl which took a single list of instructions, doing all the pipelining for you, as well as optimizing loops and assigning registers automatically. It was a godsend.

The TI-99/4A had 256 BYTES (128 words) of static RAM available to the CPU. All accesses the 16K of main memory had to be done through the video chip. This made a lot of things on the TI-99/4A slow, but there were occasional bits of brilliance where you see a tiny bit of the system it could've been. Thanks to the fast SRAM and 16-bit CPU, the smooth scrolling in Parsec was done entirely in software—the TMS9918A video chip lacking scroll registers entirely.