Thanks. Looks good! Are you aware of any 64-bit options?

Wish it was Verilog or SystemVerilog..

I've been getting tremendous use out of PicoRV32- it works, it's tiny, and for many use cases ("management plane") you just don't need much speed. I work around its slowness by providing things like relatively large communication buffers in the FPGA. I use it in "execute in place" mode from external SPI-flash (the FPGA's config flash), but with an instruction cache. It can do floating point via emulation which is handy for printf.

I've been meaning to update my toolbox to at least a pipelined processor of some sort (to up the IPC rate to at least 1), but so far just had no strong need. For applications that really need CPU power, I use SoC FPGAs like Zynq.

I've just seen a demo of a very high performance RISC-V chip (actual silicon) that'll blow the doors off other implementations. Under NDA of course.

Actually available for pre-order, take a look at the UltraRISC DP-1000 (unrelated to the chip above).

Yes, but keep in mind that I'm purposfully comparing development RTL on the open-source side with finished silicon product on the proprietary side.

Many companies have production ready/fully verified IP that are much faster than XiangShan, but they haven't taped out and productized it yet.

E.g. Tenstorrent Ascalon IP is available and at 21 SPECint2006/GHz. They want to release a lower clocked devboard on TSMC 12nm in 2026 Q2.

XiangShan is currently at 15 SPECint2006/GHz, but are targeting 22 SPECint2006/GHz in the next iteration, that is currently in the works. Well have to see who gets there first.

The inherent gap between RTL design and final product may be large enough that open-source RTL can keep up in terms of IPC, if XiangShan continues their momentum. But I think open-source trailing 1-3 years is a more realistic long term outcome.