We need more games like this so that the younger population get some sort of exposure to the hardware side of things, before AI takes over that field. I would also think that take-home electronic and soldering kits for adults and younger folks would be another way to reduce dependance on AI.
Edit: Confirmed fixed.
Really threw me for a loop! I'm still trying to wrap my head around making level 3's NOT gate.
This is such a cool idea, definitely the first 3-state circuit puzzler I've seen! Throw a cute story over it and I bet this would get some takers on Steam.
Well done and keep it up :)
otherwise, looks polished and fills in a nice niche!
That said, I'm not sure how useful expanding most of the acronyms would be. Names like Negative/Positive Metal Oxide Semiconductor aren't exactly self-explanatory, Vdd isn't really an acronym, etc..
One note: It isn't immediately obvious that the In/Out nodes can be connected to multiple wires, made the first few rounds harder to work thru.
Some comments:
- I didn't like the "truth tables" one, I got many duplicate questions and for some reason I got only one second for the first question. The rest of the questions I managed to answer correctly but I still got only one start out of three?
- I got very confused by the capacitor. Capacitors do not have an "enable" gate! In fact, in 2.7 (1T1C) you are supposed to build the enable gate -- with a transistor. So currently, you can just simply not build the enable gate and use the one already in the primitive, meaning you don't need the NMOS gate at all.
Was this made using LLM-assistence? (Not judging, I'm just interested!) I'd love to hear more about your workflow and how you managed to produce a good UI as it's something I couldn't do if my life depended on it, and it's a skill I'd like to learn.
Ill fix the truth tables bug (i think i know the issue), the stars come from playing in endless mode
I used claude quite a bit, it struggled through a lot of this (wiring and simulation systems in particular), but managed to crank this out, for the graphics i was extremely detailed in terms of what i wanted i'd say
On the capacitor though, the capacitor level is weird as you don't build the capacitor charge system with transistors. Though I definitely get that the simulation engine is for digital stuff, not analog :)
Also a general feedback on the time-based challenges: dial them back. A lot. Most of them are just not interesting and have zero learning value. In fact, the "DRAM refresh" one just made me quit the game (clicking on 8 rows to keep them fresh). Okay, 10s is enough, I got the point. No need to hold up for a whole minute. Kinda same for the hex one. However, some of them are good, and the UI for the binary ones is great, especially for the two's complement one!
Small nitpick on the UI: some blocks don't have their connections aligned with the grid, making the wiring OCD-incompatible. But that's minor. It's a shame since the wire routing algorithm works quite well overall, and I'm impressed an LLM could produce that good of an UI!
Otherwise, quite a fun little game, if slow paced when one already knows some bits of digital logic. Keep up!
Thanks, I appreciate all the feedback, fixes coming in the next push
> Wire an NMOS transistor so that when In is 1, the output is pulled to ground (0). When In is 0, the output should be unconnected (Z).
Certainly:
(a) The nMOS has 3 connections: its drain is only connected to the output (no +Vdd supply), it's source is tied to ground, it's gate is tied to the signal input
(b) When the gate (input) is driven high, the nMOS transistor turns "on," connecting the output to the source (which is grounded). This acts as a "pull-down network"
(c) When the gate is driven low, the nMOS turns "off," leaving no connection to the output. This is equivalent to a "high-impedance" / "unconnected" / "Z" output
Fails 1/2 tests
(Edit) - I thought the light grey, thick line on the background grid was a wire from "input" to the transistor's gate. It is not. You need to explicitly add a wire from "input" to gate :\
If I could make a recommendation, get rid of the grid lines entirely and only have 'dots' at regular spacing. Here's what Cadence Virtuoso looks like (the most popular circuit schematic tool for integrated circuit design):
https://www.eecs.umich.edu/courses/eecs311/f09/tutorials/cad...
I don't see any button labeled that
Ive added this to the HN Arcade! https://hnarcade.com/games/games/mvidia
also it kept showing the same table to me like 4 times
- Made timed minigames optional (e.g. binary tables)
- Added 7 (optional) intro levels to walk through pmos and nmos transistors
- Fixed the bug in the capacitor levels
- Changed editor bg to use dots instead of lines to fix wire confusion
For the PMOS, the output toggles between 1 and 0 (opposite the gate) as expected. However, for the NMOS, the output is always 0.
I don't understand why GND pulls VDD down to 0 for the NMOS, but not the PMOS.
I didn't actually finish Act 2, but it seems to end in a conventional processor with the GPU first coming after another two acts currently under construction.
nottorp•2h ago
SilentM68•2h ago