Excellent. Put me down for a couple.

Neat project - there are already a couple of good open FPGA projects. Have a look at Dirk Koch's and the FABolous teams work. They are doing exceptional work.

But all open FPGA projects miss the IO required for a good design. They do not have any serdes hardware nor DDR IO cells.

There's also an open source Authenticator software with the same name.

The gap this closes is real. IceStorm and Apicula gave you open tooling but you were still loading bitstreams onto someone else's closed fabric. Yosys/nextpnr same story. Aegis is the first time the fabric itself is auditable, which matters a lot for anyone building hardware that needs a complete trust chain from RTL down to GDS. The wafer.space + open PDK path makes it actually tapeout-able, not just a simulation exercise. Curious how the LUT4 fabric competes on density against GF180 commercial offerings, that's usually where open implementations get humbling