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Development of a transputer ISA board

https://nanochess.org/transputer_board.html
61•nanochess•2d ago

Comments

taid9iK-•1d ago
Oh my, transputers and Occam. SEQ and PAR, CHAN and whatever was there to split/assign arrays. One of my favorite go-to places when seeking peace of mind.
kragen•10h ago
Always exciting to see a new Toledo post, but this one is especially inspiring, because it talks about the author's errors that you will probably make too if you don't read the post, and tells how to overcome them. And the activity described is the highly practical activity of designing a PCB this year with the best current free software and getting it built and debugged; the fact that it's an ISA board for a Transputer is fun but not central to the problem-solving process.

I wonder why he used the 74LS00 family instead of 74HCT00, even if he really needed the TTL thresholds? I forget if ISA even requires TTL levels. Is that a question of nostalgia, or is there a practical advantage of TTL over TTL-compatible CMOS in this context that I'm unaware of?

nanochess•1h ago
The practical advantage is that the 74LS chips are available in several corner stores at 25 or 35 cents each one, and I preferred the logic to be the same family.

You cannot choose the source, these come mixed from ST, TI, and other manufacturers. I preferred the laser-engraved ones instead of the white ink ones just to have an uniform look.

The crystal oscillator needs something faster so it requires 74F04, and the link communication buffer requires 74F244 or 74AS244. These are more expensive, the 74F are 2 dollars each chip, and the 74AS are 4 dollars each chip.

webdevver•8h ago
we need to bring back the cpu address/data bus pinout on the back of PCs

i want all 64 bits with a write strobe and a 3ghz clock. let me blink leds by bitbanging /dev/mem

kragen•3h ago
That is less useful than you might expect due to issues of timing skew and signal reflections from transmission-line impedance mismatches.

SCSI was already contending with the termination problem in the early 90s; low-voltage differential SCSI was in the SCSI-3 standard from 01995, 30 years ago, in order to hit 80 megabytes per second over the kind of multidrop (bus) parallel interface you're talking about. That's twenty thousand times slower than the main system memory interface on the latest amd64 servers.

At the point where you already had to go to low-voltage differential signaling to get reliable communication, your bus is no longer a useful GPIO interface for blinking LEDs.

But if you have a 50¢ 16-line GPIO expander chip like https://www.digikey.com/en/products/detail/kinetic-technolog... somewhere on the SMBus the board is already using for things like temperature monitoring, maybe for some other minor interface function, all that's required is to run its GPIOs to test points and document them. Not as fast as the ISA bus but plenty of power for simple digital interfacing.

dboreham•2h ago
Ironic that this comment is on an article about the Transputer where the entire point was to not use memory mapped I/O, instead only p2p message channels like today's PCIe.
yjftsjthsd-h•50m ago
I think Raspberry Pis basically give you that via GPIO?
MeteorMarc•3h ago
Thanks for the pointers to the autoroute functionality in KiCAD! While wiring manually is quite satisfying, this feeling vanishes quickly when changes in the underlying schematics are required!

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Development of a transputer ISA board

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