Stanford was MIPS.
Not sure if they still use it as I graduated from there back in 2020
https://pages.cs.wisc.edu/~larus/spim.html ... and apparently its being kept up to date https://spimsimulator.sourceforge.net with new builds about every other year.
(I took the class from Professor Miller in... '92... Operating systems in... '94? 95? was from Professor Larus)
saidinesh5•7h ago
Did they all move onto using Arm these days or is RISC-V gaining traction there too these days?
chasil•7h ago
https://gf.com/gf-press-release/globalfoundries-to-acquire-m...
Edit: the article starts with the above press release.
It spends substantial time on the Nintendo 64, but not much on the "Emotion Engine" of the Sony PS2 (which was a more advanced MIPS CPU).
https://en.wikipedia.org/wiki/Emotion_Engine
There was some design oddness that plagued early MIPS and SPARC that future architectures avoided.
https://www.jwhitham.org/2016/02/risc-instruction-sets-i-hav...
One place where everyone saw the work of MIPS was the original movie Jurassic Park, on an SGI Crimson.
https://en.wikipedia.org/wiki/SGI_Crimson
meepmorp•6h ago
chasil•6h ago
It appears to have been the Godson 3, perhaps the 4000 series.
https://en.wikipedia.org/wiki/Loongson#Godson_3_/_Loongson_3...
boricj•5h ago
I wrote a Ghidra extension that can export relocatable object files. The MIPS analyzer for it is the hardest algorithmic challenge I've ever tackled, by far. The quirks of that architecture offer an endless supply of frustrating edge cases.
It uses split HI16/LO16 relocations because the earliest versions couldn't use literal pools due to a lack of PC-relative loads/stores, so figuring out pointers within the instruction stream require elaborate register dependency and code block graph traversal. Branch delay slots further scramble that instruction stream because compilers will attempt to stuff them with useful instructions. The System V ABI reference documentation for MIPS is woefully outdated and incomplete, with various extensions left undocumented.
The x86 analyzer in comparison is very straightforward. I haven't tried to add support for another RISC instruction set, but I struggle to think of one that would be even harder to deal with than MIPS (except SPARC, maybe).
Polizeiposaune•4h ago
It does delay slots by turning the PC into a two element queue so the behavior of JMP x/JMP y is well defined if mostly useless.
It also makes relatively heavy use of hi/lo splits for address constants with something like 21/11 bit splits being typical.
Also has a mechanism where most ALU instructions can conditionally trigger a skip of the next instruction based on the computed value.
And as more of a local concern that just adds friction to everything touching an instruction -- constants are sliced and shuffled into smaller bitfields within the instruction in a seemingly arbitrary way (only thing that makes sense is that the sign bit of signed constants is always in the same place in the instruction).
sitzkrieg•6h ago
microchip still has mips based pic32mz as well. i still use this in some automotive design
topspin•1h ago
I suspect there is plateau coming in the foreseeable future, as all the most desirable spectrum is fully utilized by maturing chipset designs. Should that happen, cost reduction will become a higher priority.