I do wonder if Apple‘s announcement that they started shipping it may have pushed them to announce this/agree to a standard earlier than they would have otherwise.
There is server hardware out there now that in theory can support MTE, but I don't know if there's commercial support for it. MTE needs to be set up by the firmware, it's not purely an OS/kernel matter.
Interesting thread:
https://docs.oracle.com/en/operating-systems/solaris/oracle-...
Intel had a first attempt at this with MPX, but the design had flaws,
https://en.wikipedia.org/wiki/Intel_MPX
Then there is CHERI and the related ARM Morello,
https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/
Apple isn't a first here, one first among general public.
By the way, there are already systems in place to prevent you from accessing certain memory zones. Yes, even on Linux, it's possible to make memory regions inaccessible even to root or the kernel itself. The time to be worried about that was 10 years ago.
And is everyone just expected to (metaphorically) lay down and die? You don't stop fighting for freedom just because you lost a battle... they certainly don't, and you shouldn't either!
The submission title goes "Intel and AMD standardize ChkTag ..." but the actual text says "Intel and AMD are working together, along with their ecosystem partners in the EAG, to address the need for memory safety. They are creating a unified specification ..." (emphasis mine). They don't even have a specification yet, let alone an implementation, but they want to make PR waves about it already. This is so funny (and sad).
But it wouldn’t surprise me if Apple‘s announcement they were shipping it already pushed Intel and AMD to agree on implementation details so they could announce this and get it going.
Still cool, but not a replacement for memory safety language implementations.
Even if you are using a memory safe language, memory bugs still pop up in various places (cough FFI & ABI cough) so this is a massive step in the right direction towards blocking attacks even when the developers have done "all the right things" short of formally verifying their stack from top to bottom (and even then).
I'm also tempted to write a commercial C++ compiler, but it feels like a big ask, paying for a compiler sounds ridiculous even if it reduces your compile time by 50x
How realistic is a C++ compiler that's 50x faster than clang for debug builds? Assuming 1) there's enough work for each core 2) there's so many files/headers that a unity build takes 1/4th of the time as a rebuild using individual files (this theoretical compiler would be multi-threaded)
So you’d really have to use the attack a lot for it to get patched.
Like, cool, you guys are starting to talk about a new instruction set that will make C safe somehow. Yet you failed provide an ounce of detail for how you'll accomplish that.
This might as well been a "And we'll make our CPUs 10x faster and they'll use 10x less power!". Or "Future CPUs will have a 10ghz clock speed!"
Again, who is this article for? The government maybe to assure them that x86 will take cyber security seriously?
Glad to see Tejas finally making it to see the light of day! Can’t wait to pair it with my Larrabee GPU in my BTX case.
I was convinced back in the day that Larrabee would change the world. It seemed like such an amazing technology especially since multi-core CPUs were just starting to take off in consumer hardware.
I think the problem is that Intel pigeonholed the product, relegating it to just supercomputers. I also think Intel has historically done a bad job of supporting the software needed to power their hardware.
The reason CUDA was so successful (IMO) is because it was highly available and the software is a better quality to competitive software. OpenCL was supposed to be the answer to CUDA and ultimately it was just a weird, hard to work with, and minimally supported language.
I don't think that's all Intel's fault. Apple's dumb war against Khronos has really undermined a lot of progress for anyone doing GPGPU programming.
It's a neat system with pretty much no overhead and it's pretty easy to integrate into code as long as your underlying language and libraries are at least semi-intelligent about how they handle pointers and memory allocation (i.e. as long as you aren't doing any long range pointer punting then things "just work").
https://developer.arm.com/-/media/Arm%20Developer%20Communit...
The press article is just saying what the EAG is working on next now that they have shipped FRED, ACE, and AVX10. ChkTag is the current top priority item on the EAG's list and the standard for it should be finalised/released some time in the next few months. What they have done publicly so far is to say that ChkTag will be part of the ISA standard, they just haven't also revealed the details past that.
Nothing is self contained, you are expected to look up memory tagging if you want the gory details of how other platforms implement it.
If you want technical information about how the x86 ecosystem will implement it, you'll need a time machine (or work at Intel or AMD I guess..)
But also, what you really want is ECC that reports all the way up to the OS the corrected and un-corrected bits. This is how you know if it's on the edge, becoming a real problem. Otherwise, it works fine until it doesn't shrug which is the same as regular normal memory.
I think the ECC added to the DDR5 bus is kinda just enough to get the higher data-rate signaling to be as reliable as DDR4. It's nice for marketing to put ECC on the DDR5 box but it's not more robust than DDR4.
Also, some vendors use a non-optimal hamming code that fails to notice some double bit errors (if I remember right).
Can you explain how exactly the on-die ECC capability can help protect data in transit? What is the optional functionality you're referring to, if not the traditional sideband ECC achieved by adding another chip's worth of data lines to every channel?
For a good intuition why this (coupled with instrumenting all allocators accordingly) is a game-changer for exploitation, check https://docs.google.com/presentation/d/1V_4ZO9fFOO1PZQTNODu2...
In general, having this come to x86 is long-overdue and very welcome.
The reason I'm negative is the entire article has zero detail on WTF this instruction set is or does. The best you can do is guess from the name of the instruction set.
Compare the linked iPhone article to this blog and you'll quickly see the difference. There's very real discussion in the MTE article of how the instructions work and what they do. This article just says "Memory safety is hard and we'll fix it with these new instructions that fix memory safety!"
In this particular case, it definitely does :)
IIRC, later SPARC64 chips also had a version of this.
(SPARC ADI is similar, machine code is still trusted.)
A lot of these extensions come from Intel/AMD/etc clients first, and because of how long it takes a thing to make it into mainstream chips, it was probably conceived of and worked on at least 5 years ago, often longer.
This particular thing has a long history and depending on where they worked, they know about that history.
However, they are often covered by extra layers of NDA's on top of whatever normal corporate employee NDA you have, so most people won't say a ton about it.
I'm pretty certain it'll be the x86 variant of either MTE or MIE.
There are industry partners who work closely with AMD and Intel (with on-site partner engineers etc.), but who are not represented in the x86 ecosystem advisory group, or maybe they have representation, but not at the right level. If these industry partners notice the blog post and they think they have technology in impacted areas, they can approach their contacts, asking how they can get involved.
I’m lukewarm on this.
- It is long overdue and welcome.
- It won’t stop a sufficiently determined attacker because its probabilistic and too easy to only apply partially
Is this good? Yes. Does it solve memory safety? No. But does it change the economics? Yes.
If people care a lot, I can record a YouTube video on the topic.
Previous discussion https://news.ycombinator.com/item?id=45186265
MPX had a large (greater than 15-20%) overhead and was brittle. It didn't play well with other x86 instructions and the developer experience was extremely poor (common C and C++ design patterns would cause memory faults with MPX).
Apple MIE (which is essentially ARM MTE v2) and MTE on the other hand have near invisible levels of overhead (~5-10%) with the ability to alternate between synchronous and asynchronous tracing of faults where the latter has a much lower overhead than the former (allowing you to check in production for very little overhead and get better debugging in test). They also work essentially seamlessly with the rest of the ARM ecosystem and it takes very little to integrate the functionality into any language ecosystem or toolchain.
If MPX was comparable with MTE, it certainly would have gotten the adoption that MTE is getting but the "tech" just wasn't there to justify it's use.
There's also been steady progress towards creating systems to prove unsafe rust correct - at which point it wouldn't even benefit from this. For example see the work amazon has been sponsoring to prove the standard library correct: https://github.com/model-checking/verify-rust-std/
More importantly there’s millions if not billions of existing lines of C/C++ not least of which is the VMs for “memory safe” languages like Java. There’s huge value add in automatically adding security for a fractional CPU cost since the world won’t be rewritten into Rust anytime soon.
Ada has had memory safety for decades – not to mention Lisp, Java, etc. if you can live with garbage collection. Even PL/I was better than C for memory safety, which is why Multics didn't suffer from buffer overflows and Unix did. But the Linux kernel (along with lots of other software which we would like to be reliable) is still mostly written in C, for better or worse.
To Apple's credit though they seem to be using a memory-safe language (Swift) for new code and libraries (at least at user level) and may be rewriting old code as well, and they have also added MIE/EMTE to Apple Silicon. They also ship clang/clang++ with support for -fbounds-safety and -fsanitize=address.
Objective-C also supports Automatic Reference Counting, which helps with memory management. (Apple also implemented a garbage collector for Objective-C 2.0, but abandoned it in favor of ARC. I am aware that reference counting is technically a form of garbage collection.)
The way ARC works in Objective-C, by automating retain/release call patterns already required by existing frameworks was much safer to implement, without such crashes.
Similar to all those C++ smart pointers automating COM reference counting.
Hence why Objective-C got GC, after its failure to play well with C semantics, got replaced with ARC, and afterwards Swift came to be.
Microsoft now has a new policy in place, via the Secure Future Initiative, that only exiting code bases should be kept in C and C++, all new projects are to either use managed languages or Rust.
Only with spark (i.e. formal verification). Which similar to other projects of this age (e.g. Rocq/How the compcert C compiler was implemented and proved correct) seems not to be low enough friction to get widescale adoption.
> not to mention Lisp, Java, etc. if you can live with garbage collection.
Like I said, high level languages that won't benefit from this at all have existed for ages... and the majority of software is written in them. This is one of the stronger arguments against it...
> But the Linux kernel (along with lots of other software which we would like to be reliable) is still mostly written in C, for better or worse.
Fil-C shows this can be solved at the software layer for things in this category that can afford the overhead of a GC. Which does mean a larger performance penalty than the hardware proposal, but also more correctly (since hardware changes can never solve unintended compilations resulting from undefined behavior).
The linux kernel is probably an example of an actual long tail project that would benefit from this for a reasonably long time though, since it's not amenable to "use a modified C compiler that eliminates undefined behavior with GC and other clever tricks" and it's unlikely to get rewritten or replaced with a memory safe thing quickly due to the number of companies collaborating on it.
Mainline clang and g++ are also getting better with things like -fbounds-safety and -fsanitize=address. As I understand it, they typically have some overhead, but I'm willing to accept that overhead to have a kernel, web browser, etc. without memory errors. The decision that memory safety is too costly seems to have been made when CPUs were orders of magnitude slower than they are today. Hopefully hardware support will reduce the overhead to negligible proportions and enable memory safety as a default rather than an esoteric add-on or proprietary feature.
Had UNIX and C a price tag on their source code comparable to the competition, instead of a symbolic price and an annotated source code book, history would have played a different music.
PL/I variants were being widely used, Apple was a Pascal fan, and is the company that actually created Object Pascal, not Borland.
Modula-2 was around as well, unfortunely without an OS to go to market alongside it.
The real question is, all things on equal footing regarding price, without access to source code to just type in/copy, what operating systems would people be willing to pay for.
Ada's original memory safety was still a lot better than C's. As noted, PL/I was not 100% memory safe, but it was good enough to prevent buffer overflows in Multics.
This is the first point in history where it's actually feasible in real non-research life to write an entire system in only memory safe languages. (And no, the existence of `unsafe` doesn't invalidate this point.)
Ada only has use-after-free if unchecked deallocation is used, since we are way beyond Ada83, alternatives do exist in Ada 2022.
If anything we will only get more foundational software in safer languages, when the generation that only accepts C and C++ for specific domains is no longer among us.
Unfortunately to me as well, it isn't something I will be able to witness.
You mean if you just never deallocate? Or is there a third option? Genuine question; I don't follow Ada closely.
> If anything we will only get more foundational software in safer languages, when the generation that only accepts C and C++ for specific domains is no longer among us.
I'm more optimistic - the Rust in Linux people are making progress and that's probably the thickest den of naysayers. Uutils is actually being used in Ubuntu (and sudo-rs I think?).
It'll probably take a long time until Rust outweighs C but I think we're talking 10-20 years not 30-40.
Ada provides a series of features towards that goal.
First one, already present in Ada 83, is that stack allocation is dynamic, a bit like C99 VLAs, with the differenc that it is bounds checked and and exception is thrown if there is not enough space, instead of corrupting the stack.
Also Ada pointers (access types), have some type constraints, so already with that one can make some kind of arena like storage that doesn't depend on using pointers all over the place.
Ada 95 introduced controlled types, which is basically RAII in Ada, providing yet another way not to use Unchecked_Deallocation directly on "userspace" code.
Ada 2005 introduced bounded and unbounded container types, further extended and improved in later versions, which allow to write many algorithms and data structures that build upon them, without having to go into low level memory allocation approaches.
With Ada 2012 formal proofs, coupled with SPARK 2014 tooling, you can additionally ensure specific conditions are met before doing whatever with specific resources, including ownership.
The compiler provides intrisics, has bounds checking for strings and arrays.
PL/I and its variants were also used across several systems, as were ALGOL dialects.
Note C.A.R Hoare Turing award speech in 1980,
"A consequence of this principle is that every occurrence of every subscript of every subscripted variable was on every occasion checked at run time against both the upper and the lower declared bounds of the array. Many years later we asked our customers whether they wished us to provide an option to switch off these checks in the interests of efficiency on production runs. Unanimously, they urged us not to--they already knew how frequently subscript errors occur on production runs where failure to detect them could be disastrous. I note with fear and horror that even in 1980 language designers and users have not learned this lesson. In any respectable branch of engineering, failure to observe such elementary precautions would have long been against the law."
The "1980 language designers and users have not learned this lesson" is meant to be C without explicit refering to it.
Current CPUs are limited by power, transistors are essentially free.
[1] often the VMs of safer higher level languages, in fact.
We're not, though. There's a little bit of low-level software being written in Rust (and even that requires a non-trivial amount of unsafe code), but most new low-level software is being written in C++ or C. And even if a more popular safe low-level programming language arrived tomorrow and gained a more respectable adoption, that still wouldn't be fast enough because of all the existing software.
Would this imply an architecture similar to what Lisp-Machines once had ? That'd be a great addition IMO, and would speed up a lot of dynamic-ish languages without resorting to unsafe-routes for speed.
It's scary how much of the population will suddenly shut off their brains whenever "safety and security" or similar phrases are mentioned.
sparkie•3mo ago
Presumably will be based on the existing Linear Address Masking/Upper Address Ignore specs, which are equivalent, and will be similar to CHERI.
If so it needs to be opt-in or at least opt-out per process, because many language runtimes use these pointers bits to optimize dynamic types, and would suffer a big performance hit if they were unable to use them.
monocasa•3mo ago
AFAIK, AMD only added it in Zen4.
fooker•3mo ago
pansa2•3mo ago
sparkie•3mo ago
wahern•3mo ago
PUC Lua does rely on two's complement integer representation, though, as well as long long, while nominally adhering to C90, so not quite strictly conforming.
erichocean•3mo ago
[0] https://www.youtube.com/watch?v=y_QeST7Axrw
monocasa•3mo ago
sparkie•3mo ago
Several runtimes use high bits tagging combined with NaN-boxing, and have been doing so since before LAM/UAI existed.
wbl•3mo ago
monocasa•3mo ago
themafia•3mo ago
ComputerGuru•3mo ago
vidarh•3mo ago
bluGill•3mo ago
language runtimes can call malloc whatever they want.
secondcoming•3mo ago
If you're using a custom allocator you'd have to enfore it yourself which should be fine since you have full control.
https://en.cppreference.com/w/cpp/language/alignas.html
sparkie•3mo ago
ksherlock•3mo ago
fweimer•3mo ago
C++11 already had alignas, but it was not really integrated well.
fweimer•3mo ago
afishhh•3mo ago
If you assume the top 16 bits of a pointer are unused[1], you can fit a pointer in there. This lets you store a pointer or a full double by-value (and still have tag bits left for other types!).
Last I checked LuaJIT and WebKit both still used this to represent their values.
[1] On amd64 they actually need to be sort of "sign extended" so require some fixup once extracted.
jandrewrogers•3mo ago
Using 16 bits may be risky on recent x86. For example, IIRC Linux enables 5-level page tables on microarchitectures that support it, which can put valid address data in bits 48-56.
There is no guarantee that those 6 bits are safe either. They are just the only bits for which I could not find existing or roadmap usage across x86 and ARM sources when I last did a search.
sparkie•3mo ago
Linux will not allocate past the 47-bit range, even with 5-level paging enabled, unless specifically requested, by providing a pointer hint to `mmap` with a higher address.
https://www.kernel.org/doc/html/v5.14/x86/x86_64/5level-pagi...
jandrewrogers•3mo ago
sparkie•3mo ago
Pointers need to be canonical if LAM/UAI is not enabled. The simplest way to do it is to shift left by 16, then shift arithmetic right by 16. (Or 7 if using 5-level paging). Alternatively, you can store the pointer shifted left by 16 bits, and have the tag in the lower 16 bits, then canonicalizing the pointer is just a single shift-arithmetic-right. If combining with NaN-boxing, then you rotate right to recover the double. (Demo: https://godbolt.org/z/MvvPcq9Ej). This is actually more efficient than messing with the high bits directly.
With LAM/UAI, the requirement is that the 63rd bit matches the 47th (or 56th) bit, which gives 15-bits of tag space on LAM48 and 6-bits of tag space on LAM57.
With LAM enabled, care needs to be taken when doing any pointer comparison, as two pointers which point to the same address may not be equal. There have been multiple exploits with LAM, including speculative execution exploits.
sparkie•3mo ago
sparkie•3mo ago
The high bits let us tag more types, and can be used in conjunction with low bits tagging. Eg, we might use the low bits for GC marking.
[1]:https://web.archive.org/web/20170705085007/ftp://ftp.cs.indi...
IshKebab•3mo ago
thayne•3mo ago
But that can be problematic for any code that assumes that the size of pointers is the same as size_t/usize.
I don't see how this could not be opt in for backwards compatibility though, since existing code wouldn't use the new instructions.
Tuna-Fish•3mo ago
LPDDR6 includes 16 bits of host-defined metadata per 256 bits of data. Systems can use that for ECC, and/or for other purposes, including things like tagging memory. DDR6 will likely include a similar mechanism.
SECDED ECC requires 10 bits, leaving you 6 bits. That's enough for one bit per aligned address word, which is probably used to denote "valid pointer" like CHERI.