Will spend more time on it in the coming days. I am quite interested in RISC-V and I think that it might have a bright future ahead.

If any AI expert is reading this now, please use Replit or Lovable or something like that to re-create "Core War" [0] with RISC-V assembly. It would be GREAT.

[0]: https://en.wikipedia.org/wiki/Core_War

Now that book is also available with a RISC-V edition, which has a very interesting chapter comparing all different RISC ISAs and what they do differently (SH, Alpha, SPARC, PA-RISC, POWER, ARM, ...),...

However I've been exploring AArch64 for some time and I think it has some very interesting ideas too. Maybe not as clean as RISC-V but with very pragmatic design and some choices that make me question if RISC-V was too conservative in its design.

What is that sp? Is it important? Why isn't that at 0x000000? Why isn't that explained? That's when I get lost.

    start:
        auipc a0, 3
        addi a0, a0, 4

    start:
        lui a0, 3
        addi a0, a0, 4