Don't modern NICs do a lot of the same, too?

Not at that transfer rate. SPI which is the next fastest (common) protocol you find on micros typically operates around 10 Mhz, but this isn’t an apples to apples comparison.

On a Pico? No - the PIOs replace other peripherals a µC might be able to use to achieve this sort of bitrate, so you'd not really have the tools you'd need to change GPIO pin states once every 3-4 CPU clock cycles.

In a sense the PIO is a bit 'cheaty' when claiming "bit-banging", because the PIO is the ultimate peripheral, programmable to be whatever you need. It's no mean feat to make the PIO do the sorts of things happening here, by any stretch, but "bit-banging" typically means using the CPU to work around the lack of a particular peripheral.

From that perspective, there's precious few µCs out there that could bit-bang 100MBit/s Ethernet - I'm no expert, but I _think_ that's a 125MHz IO clock, so if you want 4 CPU cycles per transition to load data and push it onto pins, you're looking for a 500MHz µC, and at those speeds you definitely have to worry about the bus characteristics, stalls, caching, and all those fun bits; it's not your old 8-bit CPU bit-banging a slow serial protocol over the parallel port any more.

Here you go, I2S output:

https://github.com/bschwind/rp2040-i2s/blob/e1d5647704b03ad1...

And I2S input:

https://github.com/bschwind/rp2040-i2s/blob/e1d5647704b03ad1...

The RP2040 has great documentation and the PIO is an amazing swiss army knife of a peripheral. I've had no trouble learning from their datasheet and docs and making plenty of PIO programs.

PIO is a set of coprocessors designed to offload signal processing. They have to be programmed. PSoC has FPGA like configuration capabilities, but rather than just logic gates it includes larger analog and digital ICs. You can route analog signal processing in and out without hitting a CPU and perform some FPGA like DSP driven by an arbitrary clock signal (also without any CPU usage).