sooner or later we get a NRAM - neural ram as extension which is basically this neuromorphic lattice that can be wired on the very low level, perhaps also photonic level, and then the whole AI thing trains/lives in it.

IBM experimenting in this direction or at least they claim to here https://www.ibm.com/think/topics/neuromorphic-computing

there is another CPU which was recently featured which has again a lattice which is sort of FPGA but very fast, where different modules are loaded with some tasks, and each marble pumps data to some other, where the orchestrator decides how and what goes in each of these.

I keep thinking of a dram with a row of MAC units and registers along the row outputs. A vector is then an entire dram row. Access takes longer then the math, so slower/smaller multi-cycle circuits could be used. This would probably require OS level allocation of vectors in dram, and management of the accumulator vector (it really should be a row, but we need a huge register to avoid extra reads and writes. The dram will also need some kind of command interface.

Memories are about density. I my memory isn't playing tricks with me, a TCAM is about ~300-400F^2 where F is the feature size of the node. On a per bit level, that means that this bit is 4E^10 bigger.

Put another way, the TLB in a CPU is relatively small and definitely a hotspot but you could estimate the TLB in a CPU at ≈ 0.0003 – 0.002 mm^2. which is ~50 times smaller then the single bit in this paper. To get to 10GHz we could just make 10 copies of an existing TLB operating at 1GHz and still have a ton of headroom. There is also a electro-optical conversion penalty that you need to take into account with most optical systems.

Not trying to be a Debbie downer. It's a cool result, no doubt incredibly useful for fully optical systems. Probably something really useful here for optical switching at the datacenter infrastructure level.