https://chimera-linux.org/news/2025/03/dropping-riscv.html

Note they eventually received a donation of CPU time that allows them to continue RISC-V support but it’s still a grim situation.

Some parts of RVA23 like a complete implementation of the vector sub-extensions, and hypervisor support, are pretty complex.[1]

If you just want RVA23 now (with poor performance) then qemu implements it. We found it's not very useful for software development, not just because it's slow, but also because it performs so differently from the real hardware, so you cannot, for example, optimize your vectorized code.

[1] I wrote a general article about RISC-V extensions last year: https://research.redhat.com/blog/article/risc-v-extensions-w...

See also: https://youtu.be/ttQtC1dQqwo

The only I can think of that may deliver earlier is Ventana with the Veyron V2, they plan to have chiplets in the first half of this year. I'm not sure if they are planning on releasing devboards though, as they target big servers. The cores have a 16 issue backend, with 5 512-bit RVV execution units (arithmetic,mask,permut,load,store) and a decode of up to 10 instructions per cycle.

See also: https://youtu.be/OPgjCjNhqKQ

Both of these claim to support full RVA23 and are high perf OoO cores.

> I bet many of its instructions will be micro coded since they aren't very useful for compilers anyway

I have listened to a lot of the talks about RISC-V and many about Vector extension, and micro-coding was barley mentioned.

What is more common is that people don't implement all the instructions in academic settings.

> Specifying standards for the future before you have working prototypes is very (ahaha) risky.

Absolutely nothing is standardized before hardware implementations exist. In fact, for Vector there was a first generation of the 0.7 that saw limited commercial use and far more more for the RVV 1.0 version.