https://developer.apple.com/library/archive/documentation/Pe...
So, when powered by AC power, schedule everything on P cores when possible, schedule processes that eat a lot of CPU on P cores, same for any process with a negative nice value.
When powered by a battery, schedule anything with non-negative nice value on E cores, keep one P core up for real-time tasks, and for nice-below-zero tasks.
These are two extremes, but I suppose that the idea is understandable.
Sometime I feel like that is undesirable. It may make system consume more power, thus more heat output and louder.
Even when plugged in, you may have thermal limitations. P cores will chew through your power budget more aggressively than E cores. For latency-sensitive workloads you do want to emphasize the P cores, but when throughput is the goal you'll usually be better off not ignoring the E cores, and not trying to run the P cores at high frequency where they're much less efficient. Intel started adding E cores to consumer chips in large part so they could score better on throughput-oriented multithreaded benchmarks like Cinebench; they're decent at compiling code, too, but you'll still want the P core for the linker.
themafia•3h ago
Really? I just bought one:
https://www.intel.com/content/www/us/en/products/sku/236786/...
pixl97•3h ago
swills•3h ago
https://en.wikipedia.org/wiki/Granite_Rapids
c0balt•2h ago
They are a bit expensive but I wouldn't expect them to drop these skews in the long term for HPC & compute bound workloads. My guess is that diamond rapids will also have some P-skews and maybe AP skews.
mlyle•57m ago
dehrmann•2h ago
wtallis•1h ago
That bit actually still applies. Intel may have branded the 14100F as Raptor Lake, but it is almost certainly Alder Lake silicon, just a higher speed bin of the 12100F.
See https://www.intel.com/content/www/us/en/products/compare.htm... and note how none of them get the higher DRAM frequency support or larger L2 caches characteristic of Raptor Lake silicon.